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Senior Mixed-Signal Verification Engineer
2 months ago
We are seeking a highly skilled Verification Engineer to join our team at Apple. As a key member of our wireless silicon development team, you will be responsible for verifying RF/Mixed-Signal blocks and SOCs using SystemVerilog.
Key Responsibilities- Design and develop testbenches, checkers, and tests for RF/Mixed-Signal blocks and SOCs
- Collaborate with architects and analog designers to review specifications and extract features
- Build and reuse real-numbered analog behavioral models, monitors, and checkers for RF/Mixed-Signal blocks
- Develop top/block level Mixed Signal and Digital testbench and generate directed and randomized tests in an SV/UVM framework
- Debug failures, fix testbench/model/checker issues, manage bug tracking, and analyze and close coverage
- Hold detailed verification reviews and set standard for coding quality
- Write scripts and define processes for increased automation of Mixed Signal verification flow
- BS and 10+ years of relevant industry experience
- Industry verification experience with RF/Mixed-Signal blocks and SOCs
- Expertise building Mixed-Signal testbenches, checkers, and tests using System Verilog
- Expertise creating and using real-numbered analog behavioral models in System Verilog/Verilog-AMS
- Experience in HVL methodology (UVM/OVM/VMM) and HDL (System Verilog, Verilog) for verification
- Strong verification skills in problem solving, constrained random testing, and debugging
- Understanding of common analog/RF blocks
- Experience with signal processing using Python or Matlab is a plus
- Experience with Virtuoso Composer, ADE, and HED a plus
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.