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Senior ASIC Digital Design Engineer
2 months ago
Synopsys is seeking a highly skilled Senior Staff ASIC Digital Design Engineer to join our Solution Group, DDRPHY IP team. As a key member of our team, you will be responsible for designing and developing world-class market-leading DesignWare DDRPHY IP solutions.
Key Responsibilities- Define and document digital microarchitectures
- Design, debug, and verify RTL logic for optimal timing, area, and power
- Collaborate with cross-functional teams to drive design innovation and excellence
- BS/MS in Electronics Engineering with at least 7 years of design experience
- Expertise in synthesizable Verilog and System Verilog design concepts and implementation
- Experience with front-end design flows, including linting, synthesis, timing investigation, and closure
- Excellent communication and self-motivation skills
- Understanding of DDR memory and DDRPHY architecture is a plus
As a Senior Staff ASIC Digital Design Engineer at Synopsys, you will have the opportunity to work on cutting-edge technologies and collaborate with a talented team of engineers. We offer a competitive total rewards package, including a base salary range of $150,000-$226,000, annual bonus, equity, and comprehensive health, wellness, and financial benefits.
Synopsys is an equal opportunity employer and welcomes applications from diverse candidates. We are committed to creating an inclusive and diverse work environment that values and respects all employees.
