Senior Timing Methodology Engineer

1 week ago

Santa Clara, California, United States NVIDIA Full time

NVIDIA is a leader in the field of artificial intelligence and high-performance computing, and we are seeking a highly skilled Senior Timing Methodology Engineer to join our team.

This role will involve developing and validating flows for PT-STA regression, analysis, and QOR metrics for high-speed designs, as well as collaborating with technology leads, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies for signing off timing in design for world-class silicon performance.

The ideal candidate will have a strong background in electrical or computer engineering, with 5 years of experience in ASIC design and timing. They will also have good knowledge of extraction, device physics, STA methodology, and EDA tools limitations, as well as a clear understanding of low power design techniques such as multi VT, clock gating, power gating, block activity power, and dynamic voltage-frequency scaling (DVFS).

Additionally, the candidate will have a good understanding of 3DIC, stacking, packing, self-heating, and its impact on timing/STA closure, as well as crosstalk, electro-migration, noise, OCV, and timing margins. They will also be familiar with clocking specs, such as jitter, IR drop, crosstalk, and spice analysis.

The successful candidate will have hands-on experience in advanced CMOS technologies, design with FinFET technology 5nm/3nm/2nm and beyond, and expertise in coding, such as TCL, Python, and C++. They will also be familiar with industry standard ASIC tools, such as PT, ICC, Redhawk, and Tempus.

This is a unique opportunity to work with a talented team of engineers and contribute to the development of cutting-edge technology. If you are passionate about timing methodology and have a strong background in electrical or computer engineering, we encourage you to apply for this exciting role.

Key Responsibilities:

  • Develop and validate flows for PT-STA regression, analysis, and QOR metrics for high-speed designs.
  • Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies for signing off timing in design for world-class silicon performance.
  • Develop tools and methodologies to improve design performance, predictability, and silicon reliability beyond what industry standard tools can offer.
  • Work on various aspects of STA, constraints, timing, and power optimization.

Requirements:

  • MS (or equivalent experience) in Electrical or Computer Engineering with 5 years' experience in ASIC Design and Timing.
  • Good knowledge of extraction, device physics, STA methodology, and EDA tools limitations.
  • Clear understanding of low power design techniques such as multi VT, clock gating, power gating, block activity power, and dynamic voltage-frequency scaling (DVFS).
  • Good understanding of 3DIC, stacking, packing, self-heating, and its impact on timing/STA closure, as well as crosstalk, electro-migration, noise, OCV, and timing margins.
  • Familiarity with clocking specs, such as jitter, IR drop, crosstalk, and spice analysis.
  • Hands-on experience in advanced CMOS technologies, design with FinFET technology 5nm/3nm/2nm and beyond.
  • Expertise in coding, such as TCL, Python, and C++.
  • Familiarity with industry standard ASIC tools, such as PT, ICC, Redhawk, and Tempus.

What We Offer:

  • Competitive salaries and a generous benefits package.
  • A dynamic and collaborative work environment.
  • The opportunity to work on cutting-edge technology and contribute to the development of innovative solutions.

How to Apply:

Please submit your application, including your resume and a cover letter, to [insert contact information]. We look forward to hearing from you.

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