Verification Engineer
4 weeks ago
SEAKR Engineering is seeking a skilled Verification Engineer to join our team. As a Verification Engineer, you will be responsible for developing verification and simulation strategies, creating digital test plans, and providing coverage metrics.
Key Responsibilities:- Develop verification and simulation strategies to ensure design quality and reliability
- Create digital test plans and provide coverage metrics to measure test effectiveness
- Construct and maintain simulation environments using System Verilog with UVM (Universal Verification Methodology)
- Perform and evaluate regression tests for designs under test
- Extract and derive test requirements and sequences from design documentation and requirements
- Bachelor's degree in Electrical Engineering or Computer Science
- Master's degree preferred
- 0-3 years of verification engineering experience
- Ability to analyze and write System Verilog
- Ability to diagnose sophisticated test failures and file results
- Ability to analyze code coverage and adjust agent sequence behavior
- Ability to use simulation tools such as Mentor Graphics Modelsim/Questasim for simulation debug and reporting
- Base salary range: $80,000-95,000 depending on qualifications
- Rich medical, dental, and vision insurance plans
- Generous 401(k) retirement plan
- Year-end bonus
- Paid leave, including vacation, sick, bereavement, and FMLA
SEAKR is an Equal Opportunity Employer. All applicants will be considered without regard to race, color, religion, sex, national origin, age, disability, or any other protected characteristic. US Citizenship is required.
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