Lead RTL Microarchitect

2 weeks ago


California, United States DAC Search Inc Full time

Company Overview

DAC Search Inc, led by Richard Goldstein, specializes in recruitment services tailored for the Semiconductor, EDA, and AI Chip sectors, focusing primarily on innovative startups.

About the Client

Our client is at the forefront of developing essential technologies for chiplet-based semiconductor design. As an early-stage startup, they are pioneering advancements in the multi-chiplet system-on-package paradigm. Their mission is to drive the next wave of growth within the semiconductor industry, and they are seeking passionate professionals to join their experienced and dynamic team. The founding members have a proven track record, having successfully led a previous startup that was acquired by a major chip company, which lends them significant credibility in the field. The executive team and board are exceptionally strong.

Position Overview

We are looking for a seasoned RTL Microarchitect who thrives in startup environments and is excited about the challenges that come with it. This role requires on-site presence, fostering a cohesive team dynamic.

Key Responsibilities

  • Design and develop microarchitectures for a range of highly configurable IPs.
  • Implement microarchitecture and RTL coding to ensure optimal performance, power efficiency, and area utilization.
  • Collaborate with software teams to establish configuration requirements and verification collateral.
  • Engage with verification teams on assertions, test plans, debugging, and coverage analysis.

Qualifications and Preferred Skills

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science.
  • A minimum of 8 years of hands-on experience in microarchitecture and RTL development.
  • Proficiency in Verilog and System Verilog.
  • Familiarity with industry-standard EDA tools and methodologies.
  • Experience with large, high-speed, pipelined, stateful designs, as well as low-power designs.
  • In-depth knowledge of on-chip interconnects and NoCs.
  • Experience with ARM ACE/CHI or similar coherency protocols.
  • Experience in designing IP blocks for caches, cache coherency, memory subsystems, interconnects, and NoCs.
  • Familiarity with RAS designs, QoS in fabrics, and PCIe/IO is advantageous.
  • Experience with modern programming languages such as Python is a plus.
  • Exceptional problem-solving abilities and attention to detail.
  • Strong communication and collaboration skills.

We encourage interested candidates to apply directly through our platform.



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