Senior FPGA Design Engineer

4 days ago


San Jose, California, United States Teradyne Full time
About the Role

We are seeking a highly skilled Senior FPGA Design Engineer to join our global technology company, Teradyne. As a key member of our team, you will play a crucial role in developing innovative solutions for complex testing challenges.

Key Responsibilities
  1. Design and Implementation: Architect and implement FPGA solutions to support next-generation Flash and DRAM test instrumentation, ensuring high-quality and reliable designs.
  2. Technical Leadership: Provide technical guidance and leadership to junior engineers, fostering a collaborative and innovative work environment.
  3. Concept to Reality: Translate abstract concepts and customer requirements into practical, extensible, and supportable designs, driving product development and quality improvement.
  4. Design Maintenance and Extension: Assist in the maintenance and extension of existing FPGA designs to support emerging customer requirements and quality improvement initiatives.
  5. Project Delivery: Ensure timely delivery of high-quality end products, meeting schedule commitments and customer expectations.
  6. Travel and Collaboration: Participate in occasional travel to collaborate with cross-functional teams and stakeholders, driving innovation and growth.
Requirements and Qualifications
  1. Digital Design Expertise: Proven experience with digital design and architecture, including RTL coding, synthesis, timing closure, and lab validation.
  2. Technical Skills: Strong proficiency in Static Timing Analysis of ASICs or FPGAs, digital simulation testbench creation, and C or C++ programming.
  3. Lab Equipment Familiarity: Familiarity with lab equipment such as oscilloscopes, power supplies, and waveform generators.
Desired Skills and Qualifications
  1. FPGA Transceiver Design: Experience with FPGA transceiver-based design, including DRAM and Flash Memory interfaces.
  2. Intel/Xilinx FPGA Tool Flows: Familiarity with Intel/Xilinx FPGA tool flows and Verilog HDL Language.
  3. UVM Methodology: Proficiency with UVM (Universal Verification Methodology) and Linux/Windows operating systems.
  4. ATE Instrumentation: Familiarity with ATE (Automatic Test Equipment) instrumentation and its applications.
Education and Experience

Bachelor's or Master's degree in Electrical Engineering or a closely related field, with a minimum of 8 years of relevant work experience in FPGA design and development.



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