Senior Low Power Logic Design Engineer

2 weeks ago


Cupertino, California, United States Apple Full time
Job Title: Senior Low Power Logic Design Engineer

At Apple, we're committed to innovation and excellence in all aspects of our business. We're seeking a highly skilled Senior Low Power Logic Design Engineer to join our team and contribute to the development of cutting-edge wireless communication systems.

Key Responsibilities:
  • Design and implement power management logic for complex wireless communication SoCs
  • Collaborate with cross-functional teams to verify and debug power management logics
  • Work with the Power team to analyze and optimize power consumption
  • Develop and maintain technical documentation and specifications
Requirements:
  • Proven track record in power/clock management logic design
  • Proficiency in Verilog language
  • Experience with SoC level power management logic verification and debug
  • Deep understanding of ASIC low power design techniques
  • Knowledge of CDC, RDC, and UPF and its VCLP checker
  • Strong problem-solving skills
  • Proficiency in scripting languages, e.g., Unix shell, Perl, or Python
Preferred Qualifications:
  • BS and 10+ years of relevant industry experience
  • SoC top-level integration experience
  • SW team support experience
  • System architecture knowledge
  • Post-silicon debug experience
What We Offer:
  • Competitive base pay between $175,800 and $312,200
  • Discretionary restricted stock unit awards
  • Employee Stock Purchase Plan
  • Comprehensive medical and dental coverage
  • Retirement benefits
  • Discounted products and free services
  • Reimbursement for certain educational expenses

Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.



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