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Senior Low Power Logic Design Engineer

2 months ago


Cupertino, California, United States Apple Full time
Job Summary

We are seeking a highly skilled Senior Low Power Logic Design Engineer to join our Wireless SOC organization. As a key member of our team, you will be responsible for designing power management logics for complex wireless communication SoCs.

Key Responsibilities
  • Define and write specifications to cover SOC power management features to meet product requirements
  • Implement power management logic
  • Collaborate with DV, FPGA, and other teams to verify power management logics
  • Work with the Power team for power analysis work
  • Post-silicon power management feature debug
  • Support the Power team in performing power correlation
Requirements
  • Proven track record in power/clock management logic design
  • Proficiency in Verilog language
  • SoC level power management logic verification and debug experience
  • Deep understanding of ASIC low power design techniques
  • Knowledge of CDC, RDC, and UPF and its VCLP checker
  • Strong problem-solving skills
  • Proficiency in scripting languages, e.g., Unix shell, Perl, or Python
  • SoC top-level integration experience is a plus
  • SW team support experience is a plus
  • System architecture knowledge is a plus
  • Post-silicon debug experience is a plus
What We Offer

At Apple, we offer a comprehensive compensation package, including a base pay range of $175,800 to $312,200, and the opportunity to become an Apple shareholder through our discretionary employee stock programs. We also provide benefits such as comprehensive medical and dental coverage, retirement benefits, and a range of discounted products and free services.