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Digital Design Engineering Lead
2 months ago
At Analog Devices, we're pushing the boundaries of innovation to create a better world. As a Principal Digital Design Engineer, you'll be part of our Central Digital IP team, responsible for developing and delivering reusable strategic IPs to accelerate product development across the company.
Key Responsibilities:- Architect and design key digital blocks, such as accelerators and datapath IP, with built-in configurability for power, performance, and area tradeoffs.
- Develop a strong understanding of heterogeneous processor cores and subsystems, including A55, M55, M4, U55, RISC-V, and DSP core, and their integration requirements.
- Consolidate and curate digital IP for SPI, I2C, UART, JTAG, and other slow serial interfaces and peripherals.
- Evaluate 3rd party IPs on power, performance, area, and other key qualitative aspects, and make recommendations.
- Build deep expertise on complex interfaces, peripherals, and protocols, such as DDR, Ethernet, eMMC/SD, MIPI, Display Port, HDMI, PCIe, and high-speed D2D.
- Packaging digital IP for seamless integration into design flow at different stages, including RTL, constraints, CDC waivers, timing wavers, DFT DRCs, and waivers.
- Develop and maintain a catalog of digital IPs to enable ease of information sharing to customers across different BUs.
- Develop user guides for RTL integration, synthesis, DFT, PnR, programming sequence, characterization, and evaluation flows.
- Minimum B.E./B.Tech degree in Electrical/Electronics/Computer Science.
- 5-12+ years of digital logic design and hands-on RTL coding experience using Verilog and SystemVerilog.
- Strong understanding of control path and data-path digital design concepts with an eye for realizing correct-by-construction solutions.
- Experience with specifying Design Verification (DV) requirements, such as test plans, coverage metrics, and evaluating DV quality to realize robust design quality.
- Knowledge of Lint, CDC, formal equivalence, DFT concepts, power analysis, and developing timing constraints.
- Ability to technically mentor a few junior engineers.
- Good interpersonal, teamwork, and communication skills to logically and effectively drive discussions with teams spread geographically.
- Understanding of standard on-chip interfaces, such as APB/AHB/AXI/Stream protocols, and knowledge of Processor/SoC architecture and/or DSP fundamentals are strong pluses.
- Experience with end-to-end ASIC/SoC product development and productization is very desirable.
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