Senior Physical Design Engineer

1 month ago


Santa Clara, United States Astera Labs Full time

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of cloud and AI infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL and Ethernet semiconductor-based solutions based on a software-defined architecture that is both scalable and customizable. Inspired by trusted partnerships with hyperscalers and the data center ecosystem, we are an innovation leader of products that are flexible, interoperable, and reliable. We are headquartered in the heart of California’s Silicon Valley, with R&D centers and offices in Taiwan, China, Vancouver and Toronto, Canada, and Haifa, Israel. 

Basic qualifications:

  • Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred.
  • ≥10 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. 
  • Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind

Required experience:

  • Hands-on and thorough knowledge of synthesis, place and route, timing, extraction and other backend tools and methodologies for technologies 16nm or less.
  • Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level.
  • Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production.
  • Experience with Cadence and/or Synopsys physical design tools/flows.
  • Familiarity and working knowledge of System Verilog/Verilog.
  • Experience with DFT tools and techniques.
  • Experience in working with IP vendors for both RTL and hard-mac blocks.
  • Good scripting skills in python or Perl

Preferred experience:

  • Good knowledge of design for test (DFT), stuck-at and transition scan test insertion.
  • Familiarity with DFT test coverage and debug.
  • Familiarity with ECO methodologies and tools.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.



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