RTL Design Engineer

Position Title: RTL Design Engineer Position Description: Protingent Staffing has an exciting contract opportunity for RTL Design Engineer with our client located in San Jose, CA.Project Description: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write...

KEY RESPONSIBILITIES: • Microarchitecture development of IP subsystems • Perform RTL design of digital components. • Work with functional verification team to meet coverage and quality standards. • Analyze/fix Lint and CDC errors of the components. • Guarantee quality/timely deliverables meeting project’s schedule. • Help to improve/automate...

JOB DESCRIPTION: JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for linting and simulation of design. Work with synthesis and backend teams for physical...

KEY RESPONSIBILITIES: • Microarchitecture development of IP subsystems• Perform RTL design of digital components.• Work with functional verification team to meet coverage and quality standards.• Analyze/fix Lint and CDC errors of the components.• Guarantee quality/timely deliverables meeting project’s schedule.• Help to improve/automate design...

KEY RESPONSIBILITIES: • Microarchitecture development of IP subsystems• Perform RTL design of digital components.• Work with functional verification team to meet coverage and quality standards.• Analyze/fix Lint and CDC errors of the components.• Guarantee quality/timely deliverables meeting project’s schedule.• Help to improve/automate design...

KEY RESPONSIBILITIES: • Microarchitecture development of IP subsystems• Perform RTL design of digital components.• Work with functional verification team to meet coverage and quality standards.• Analyze/fix Lint and CDC errors of the components.• Guarantee quality/timely deliverables meeting project’s schedule.• Help to improve/automate design...

Location: San Jose, CA - Hybrid (at least 3 days a week) KEY RESPONSIBILITIES: Microarchitecture development of IP subsystems Perform RTL design of digital components. Work with functional verification team to meet coverage and quality standards. Analyze/fix Lint and CDC errors of the components. Guarantee quality/timely deliverables meeting project's...

THE DUTIES:The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and client s internal IPs.Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes.Our RTL Design Engineers are expected contribute in all aspects of SoC...

Description:• Microarchitecture development of IP subsystems• Perform RTL design of digital components.• Work with functional verification team to meet coverage and quality standards.• Analyze/fix Lint and CDC errors of the components.• Guarantee quality/timely deliverables meeting project’s schedule.• Help to improve/automate design...

ASIC/RTL Design Engineer Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural...

Job Title: RTL Design Engineer - Senior Work Location: Santa Clara, CA 95054 Duration: 12 Months Work Type: Contract Job Type: Onsite Pay Rate: $78.00-78.00/Hourly/W2 Overview: TekWissen Group is a workforce management provider throughout the USA and many other countries in the world. This Client is an American multinational semiconductor company based...

RTL Design Engineer - Specialized (US) 12 months contract (W2) Location: San Jose, CA 95124. Hybrid (at least 3 days a week onsite)Job Description:Location: San Jose, CA - Hybrid (at least 3 days a week)KEY RESPONSIBILITIES: • Microarchitecture development of IP subsystems • Perform RTL design of digital components. • Work with functional...

Job Description: Pay Range $ 70.86hr - $75.86hr Responsibilities: Perform RTL design of digital components in Verilog/systemverilog. nalyze/fix Lint and CDC errors of the components. Guarantee quality/timely deliverables meeting project's schedule. Help to improve/automate the design process. Preferred Experience: Knowledge of RISK-V...

Location: Onsite San Jose, CA JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for linting and simulation of design. Work with synthesis and backend teams for physical...

ASIC/RTL Design Engineer Location:Santa Clara, CA Posted On: 03/15/2024 Requirement Code: 67337 Requirement Detail JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and AMD internal IPs. Successful candidates will be responsible for leading, and participating in, the design of...

Location: Onsite San Jose, CA JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for linting and simulation of design. Work with synthesis and backend teams for physical...

Location: Onsite San Jose, CA JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for linting and simulation of design. Work with synthesis and backend teams for physical...

Location: Onsite San Jose, CA JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for linting and simulation of design. Work with synthesis and backend teams for physical...

KEY RESPONSIBILITIES: • Microarchitecture development of IP subsystems • Perform RTL design of digital components. • Work with functional verification team to meet coverage and quality standards. • Analyze/fix Lint and CDC errors of the components. • Guarantee quality/timely deliverables meeting project's schedule. • Help to improve/automate...

KEY RESPONSIBILITIES: • Microarchitecture development of IP subsystems • Perform RTL design of digital components. • Work with functional verification team to meet coverage and quality standards. • Analyze/fix Lint and CDC errors of the components. • Guarantee quality/timely deliverables meeting project's schedule. • Help to improve/automate...