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Design Verification Engineer

2 months ago

Santa Clara, United States CV Library Full time

Job Description

Role: Design Verification Engineer

Work Location: Santa Clara, CA

Interview: Phone/Skype

Job Type: Contract

UVM/OVM/SystemVerilog/Python/C/C++

Responsibilities:

• Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces.

• Develop test plans and coverage metrics from specifications and writing block and chip-level tests.

• Create PERL/Python scripts to automate creating verification environments, tests

and debugging.

• Failure analysis of Register Transfer Level and Gate simulations and resolve them by working with design engineers.

• Create low power testcases using UPF or CPF to verify the desired power intent of the SoC.

• Work with architects to determine the use-case scenarios to simulate

Qualifications:

• 7+ years of experience in pre-silicon design verification

• Proficiency in C-shell scripting, Verilog-HDL & System Verilog.

• Strong knowledge in SV Assertions, UVM/OVM and functional code coverage.

• SOC Verification experience using ARM Cortex Microcontroller is required.

• Experience with advanced peripheral bus Verification IP’s such as GPIO, UART, SPI, SW, JTAG, and I2C.

• Proficient with Cadence tools such as NCVerilog, NCSIM, Simvision. Experience with linting tools (i.e Spyglass) will be helpful.

• Exposure to SDF annotated simulations with good understanding of parasitic delays and timings is required.

• Exposure to FPGA programming and FPGA tools will be helpful.

• Independent, self-motivated with good analytical & communication skills.

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