Wireless PHY ASIC Design Engineer

5 days ago

San Jose, United States Spreadtrumusa Full time

Wireless PHY ASIC Design Engineer (All levels) As a member of our engineering team, you will work on the latest WLAN technology and product development. Successful candidates will be participating in the design of leading edge ASICs for Wireless Connectivity SoC platform. We currently have multiple openings for various levels, check below for details and apply today Responsibilities PHY ASIC design engineer is responsible for the design and implementation of WiFi Baseband modem. Duties include, but are not limited to: Architect and develop state of the art microarchitecture of various processing blocks in WiFi PHY hardware based on signal processing algorithm, including baseband modem design, interface design to RF subsystem, MAC subsystem and SoC. Implement and deliver PHY RTL design according to fixed-point reference model, assist the synthesis, timing and power analysis. Develop unit-level verification and support bi-true verification with reference model, work with DV engineer for integrated-level verification. Lint, CDC check. Assist in all different level of ASIC simulation. Support FPGA prototyping or SoC Lab validation. Experience KNOWLEDGE, SKILLS, & COMPETENCY REQUIREMENTS Knowledge of 802.11 (11b/a/g/n/ax/ax/be) WiFi PHY baseband spec is desired. Knowledge of wireless baseband DSP algorithm and ASIC implementation. Must have experience of fixed point digital design and RTL implementation. Familiar with ASIC flow from micro-architecture development, RTL coding, CRC/RDC, power analysis, Synthesis and STA and timing closure, to final tape-out and production support. Expertise in verification and validation of signal processing ASICs is required. Desired PHY ASIC implementation experience include FEC Decoder, Beam-Forming, MIMO Channel Estimation and equalization, Channel Smoothing, Noise Whitening, FFT, DFE and digital filters. Experience of low power design. The following traits are highly valued: Knowledge of wireless communication system such as WiFi, Bluetooth, UWB, 4G LTE and 5G NR is a plus. Advanced wireless communication techniques including MIMO OFDM/OFDMA system design, signal acquisition, synchronization, and equalization, advanced error correction techniques is a plus. Experience of SoC architecture, on-chip SoC bus protocol, framers/deframers and data movers, CPU/DSP architectures and embedded subsystems is a plus. Familiarity with RFIC architecture is a plus. Location San Jose Full Time Additional EDUCATION & EXPERIENCE Minimum years of applicable work experience for: #J-18808-Ljbffr

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