Lead DFT Engineer

4 weeks ago

Mountain View, United States Understanding Recruitment Full time

Acceler8 Talent has recently partnered with a company that is redefining AI hardware, focusing on maximizing performance for large language models (LLMs) like GPT. With a commitment to cost efficiency and optimizing performance-per-dollar, their technology offers competitive latency and low-level hardware control. Their scalable hardware enables faster model development and accessibility for researchers and startups. Founded by two previous leaders of a FAANG company, they are leading the charge as the compute platform for AGI, crafting comprehensive solutions from silicon to systems. They are actively looking for a Lead DFT Engineer. Responsibilities: Take charge of their DFT methodology and collaborate on silicon and physical design approaches across various levels, ensuring scalability from RTL to GDS. Design the DFT solution, including memory and logic testability for large and complex silicon, utilizing leading industry tools and flows. Optimize DFT implementation at block and subsystem levels, selecting top-level control structures for efficiency and coverage. Lead reviews and track progress towards silicon milestones, including design freeze and tapeout. Coordinate with design, verification, and physical design teams to ensure optimal DFT performance, power, and area results. Manage design services partners and third-party vendors for block-level and chip-level DFT planning and execution. Collaborate with Operations, foundry, and test partners to implement test programs on silicon and achieve production and NPI coverage goals. Requirements: Architecture-to-production experience in driving DFT strategy and execution on large and complex ASICs and SOCs to production silicon Production-proven experience with deploying DFT at-scale for large and high-performance ASICs and SOCs in both pre0-silicon implementation and post-silicon test program completion for NPI Project experience in collaborating with design, verification and physical design teams to structure and partition the design optimally for PPA and sign-off Experience in working with a third-party design services partners to deliver tapeout-ready designs with DFT Experience with test engineering partners and taking test programs from bring up to volume production Experience with FA (Failure Analysis) and debugging failures on silicon with design and verification teams If interested in joining them please apply here or reach out to Jwhitcomb@acceler8talent.com

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