DFT Engineer

1 week ago

Mountain View, United States Acceler8 Talent Full time

DFT Engineer

Join an experienced team of silicon and distributed systems experts at this startup, pioneering groundbreaking solutions for next-generation computing workloads. With a track record of powering over half of today's global data center traffic, they're developing a fabric that doubles the IO per dollar compared to competitors. Backed by a significant investment, this team, led by industry veterans, is set for rapid growth.

As a Design For Test engineer, you'll play a vital role in revolutionizing the performance and scalability of distributed computing systems. Whether in Mountain View, CA, or remote, talented candidates with experience in large-scale networking and computing chips are welcome to join this dynamic environment.

Job Description: DFT Engineer

Responsibilities

  • The DFT engineer will collaborate with cross-functional teams to implement cutting-edge designs in test access mechanisms, IO BIST, memory BIST, and scan compression.
  • They will partner with third-party IP vendors to integrate Memory BIST, scan, PHY I/O BIST, and other DFT logic into a streaming scan fabric with a sequential scan compressor/decompressor.
  • They will collaborate with DFT Solutions Vendors to port patterns at the top level, implement the Memory BIST interface in high-performance processor IP, and implement high-speed I/O for logic scan tests.
  • They will coordinate with Physical Designers to validate DFT timing constraints.
  • They will work alongside RTL Designers to verify test design rules.
  • They will team up with Test Engineers to bring up patterns on Automated Test Equipment (ATE).
  • They will contribute to the development and deployment of DFT methodologies for next-generation products.

Qualifications

  • MSEE or equivalent experience.
  • 7+ years of experience in DFT or related domains.
  • In-depth knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG, and fault simulation.
  • Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools.
  • Good exposure to cross-functional areas including RTL and clocks design, STA, place-and-route, and power to ensure optimal trade-offs.
  • Experience in silicon debug and bring-up on ATE, with an understanding of pattern formats, failure processing, and test program development.
  • Strong programming and scripting skills in Perl, Python, or Tcl are desired.
  • Exceptional written, oral, and interpersonal skills, along with the curiosity to tackle unique challenges.

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