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Design Verification Engineer

2 months ago

New York, United States QuEST Global Full time

Job description Create verification plans for complex processor systems and IP blocks Create testbenches in SystemVerilog with UVM Utilize advanced verification techniques Write tools and scripts to enhance the verification process Qualifications and requirements: 4+ years industry experience required. BS, MS in computer science or engineering Experience with C/C++ Experience with SystemVerilog and UVM Knowledge of AXI, APB, AHB and other bus protocols Some level of processor-based verification Experience with advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verifiers. Experience with tools for regression management, configuration management and bug tracking UPF simulation experience is plus. Any emulation, prototyping, post silicon debug experience is plus. GLS debug and bring up experience is plus. Understanding of overall ASIC/SOC architecture is plus. Good software skills Good problem solving and debugging skills.