Senior Physical Design Engineer

4 weeks ago

Portland, United States Microsoft Corporation Full time

Microsoft Corporation Senior Physical Design Engineer Portland, Oregon Apply Now Microsoft Silicon, Cloud, Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission. As Microsoft's cloud business continues to grow, the ability to develop new generation silicon is of paramount importance. To achieve this goal, Microsoft’s Cloud Compute Development Organization (CCDO) is seeking a passionate, driven, and intellectually curious engineer to join our silicon hardware physical design team, covering RTL to GDS methodology, design convergence, and design quality for our projects. We are responsible for delivering cutting-edge, CPU-based custom SOC designs that can perform complex and high-performance functions in the most efficient manner. This team will be involved in numerous projects within Microsoft developing CPU based SOCs silicon for data centers. We are looking for a Senior Physical Design Engineer to join the team. In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day. Responsibilities Own execution from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff, Formal Equivalence, and Low Power Verification. Responsible for Timing & Power critical IPs’ execution with PPA (Power, Performance and Area) focused. Responsible for RTL to GDS implementation in Physical Design domain. Coordinate with CAD, RTL/Design teams, Architecture team, Power & Performance team, Technology team & other internal/external partners. Lead & Influence in TFM (Tools, Flows, and Methodology) & PPAS (Power, Performance, Area & Schedule) for design construction to signoff. Demonstrate technical expertise across various domains of Physical Design & Timing Signoff (E2E). Clear communications on project status & planning. Collaborate across various geographic locations based on need. Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion. Qualifications Required Qualifications: 7+ years of related technical engineering experience OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. 7+ years of experience in semiconductor design. Other Requirements Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter. Preferred Qualifications: BS/MS in Electrical or Computer Engineering or any related degree Large SoC/CPU/IP design tape-out experience in the latest foundry process nodes. Own complete PD execution of challenging Timing & Power critical projects. Understanding of constraints generation, STA, timing optimization, and timing closure. In-depth understanding of design tradeoffs for power, performance, and area (PPA). Physical Design experience in synthesis to place and route of partitions through all sign-off including timing sign-off, physical verification, EMIR sign-off, Formal Equivalence, and Low Power Verification. Analyzing Power, Area, and Timing (PPA) trade-offs for new tech nodes & enabling project level decisions. Hands-on experience with CTS and global clock distribution methods in multi-voltage & power domain, multi-clock, and low power designs. Experience and knowledge of formal equivalency checks, LEC, FEV, LP, UPF, reliability, SI, and Noise. Experience in EDA tools such as Synopsys, or Cadence. Exposure and some hands-on experience with PD flows bring up/setup/flow flush, overall know how of PD-TFM and PD methodology is a big plus. Collaborating and influencing various aspects of PD Methodology focused on PPA. Proven understanding of PD construction & analysis flows and methodology. Understanding of constraints generation, DFT timing modes, STA analysis, Timing optimization, and Timing closure. Experience and knowledge of formal equivalency checks, LP, UPF, reliability, SI, and noise analysis. Knowledge on ECO implementation for formality and Power/Timing convergence. Automation skills using scripting languages such as Perl, TCL, or Python. Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. #J-18808-Ljbffr

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