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Senior Staff Physical Design Engineer
1 month ago
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise and execution, Marvell's custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you'll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance chips. Our vision is to enable Compute & Storage solutions for AI, data center, and communication infrastructure. What You Can Expect In this hybrid role based in Santa Clara, you will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process. Every day, you'll be working hands-on to triage workflows, whether you're running RTL code through synthesis and place and route (PnR) tools to create the physical view of the chip, analyzing performance by running timing analysis, verifying a robust power grid by performing EMIR analysis, especially on complex IP such as DDR, PCIe, etc. You will work closely with top level PD engineer, timing engineer, DFT engineer, and RTL designers. There are many sign-off checks that need to happen to verify that the database is ready to move on to the next level, and it's your responsibility to review completed runs for errors or create optimizations from successful runs. There are opportunities for potential customer interfacing. What We're Looking For Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience. Or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience. Candidate should have good knowledge on PnR and have handled complex blocks using latest technology nodes like 7nm, 5nm, 3nm. Should have exposure in multiple tool usage across Cadence/Synopsys platforms: Innovus/FC Knowledge of static timing analysis and synthesis Skilled knowledge on scripting language i.e. Python, Tcl, Perl Effective communication, verbal, and written skills Partition-level / multi-hierarchy experience is a plus #J-18808-Ljbffr
