Digital Design Verification Engineer

2 days ago

San Francisco CA, United States Amadeus Search Full time

Design Verification Engineer – Internal IP
A fast-growing AI startup designing next-generation compute hardware. The company specializes in building high-performance IP blocks and accelerators, aiming to enable leading‑edge AI workloads with custom silicon and software stacks.
You will lead verification efforts on internal IP blocks that power the company’s compute architecture. Working closely with design engineers and systems teams, you’ll define verification strategies, develop testbenches, write directed and random stimulus, debug failures, and sign off quality IP for integration into larger systems.
Review IP specifications and architecture to understand functional, performance, and integration requirements.
Automate regressions, monitor coverage metrics, identify gaps, and work with design teams to close them.
Debug and triage simulation/emulation failures, analyze waveforms/traces, provide meaningful feedback to design and physical teams.
Collaborate with RTL designers, synthesis and physical teams, CAD and systems/firmware teams to ensure smooth handoff and tape‑out readiness.
Mentor or collaborate with other engineers to drive verification best practices and process improvements.
Strong experience (typically 5 + years) in design verification of digital IP in a hardware environment.
Deep understanding of digital logic, microarchitecture (e.g., pipelines, memory subsystems, AXI/AMBA interconnects), timing, and clocking domains.
Bachelor’s or Master’s in Electrical Engineering/Computer Engineering or equivalent; Experience in AI/hardware accelerator domain (e.g., tensor cores, matrix engines, AI pipelines).
Familiarity with low‑power design, clock gating, power domains, and verification of power/clock islands.
Experience working with mixed‑signal or analog/mixed‑signal IP verification, or prototyping on FPGA/emulation platforms.
Opportunity to design and verify cutting‑edge compute IP for AI workloads.
Competitive compensation, equity participation and benefits aligned with high‑growth startup norms.

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