Physical Design Power Integrity Flow Development Engineer
4 weeks ago
Role: Physical Design-Power Integrity Flow Development Engineer
Location: Phoenix, AZ
Experience: 9 years
Job Description
- Perform comprehensive power analysis in vector and vector-less modes of ASIC SoC design at different design stages from RTL to gate-level netlist.
- Develop & own power grid implementation of multi hierarchy low power designs including power analysis, IR Drop, EM, IR drop based STA in advanced technology nodes (5nm and below).
- Resolve power & power integrity issues related to physical design, identify potential low power solutions, drive execution and methodology improvements.
Basic Qualifications:
- RTL2GDSII design flow usage & development in advanced technology nodes (7nm and below)
- Low power implementation and signoff, power gating, multiple voltage rails, UPF/CPF usage.
- Power grid design & implementation o Power integrity analysis at block and top level, including EM, IR & ESD analysis, power reduction techniques in SOC design.
- Power constraints generation and validation, power analysis, interface with power integrity analysis tools such as thermal analysis. o Strong expertise in Python & TCL programming.
- EDA tools including Redhawk/Voltus , DesignCompiler/Genus, Primetime/PrimePower/Joules, FusionCompiler/ICC2/Innovus
- Bachelor's degree in Electrical Engineering or Computer Science.
Preferred Qualifications:
- Experience running power analysis in vector and vector-less modes and achieving optimal QoR on low power designs.
- Knowledge of static timing analysis, low power concepts, defining timing and power constraints exceptions, switching activity definitions and simulation vectors generation & usage
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