Design Engineer

4 weeks ago

Phoenix, United States Mastech Digital Full time

Job Title: Physical Design Engineer

Duration: 6+ months

Location: Phoenix AZ 85004

Job Description:

  • Electrical Engineering - Design Integrated Circuits (IC) that power everyday electronic devices. Design custom or semi-custom silicon used on electronic devices, cloud infrastructure, machine learning, and AI computational platforms.
  • Work across the entire silicon design lifecycle, including system architecture, design verification, RTL digital design, physical design, design for test (DFT), and Emulation.
  • Education - BS in Computer Science or Electrical Engineering
  • Vaccination mandate - Yes
  • 3-7 years experience in semiconductor design and development.

Must-have skills for this role - Years of experience required for each skill- 3-7 years experience.

  • Electrical Engineering
  • Electronic Design Automation (EDA)
  • Semiconductor Design & Development

Nice-to-have skills:

  • Experience running power analysis in vector and vector-less modes and achieving optimal QoR on low power designs.
  • Knowledge of static timing analysis, power analysis and concepts, defining timing and power constraints exceptions, switching activity definitions and simulation vectors.
  • Experience with power integrity analysis at block level or top level, including EM, IR & ESD analysis, power reduction techniques in SOC design.
  • What are the chances for extension? 100%, purely based on performance.

The Work:

  • Develop own physical design implementation of multi hierarchy low power designs including physical aware logic synthesis, design for testability, static timing analysis, power analysis, IR Drop, EM, in advanced technology nodes
  • Resolve power issues related to physical design, identify potential low power solutions, drive execution and methodology improvements.
  • Perform comprehensive power analysis in vector and vector-less modes of ASIC SoC design.

Heres what you need/ Job Description:

  • A minimum of three years of experience with:
  • RTL2GDSllon advanced technology nodes (7nm and below)
  • Low power implementation and signoff, power gating, multiple voltage rails, UPF/CPF.
  • Power constraints generation and validation, power analysis, interface with power integrity analysis tools.
  • TCL, Python and/or Perl programming
  • EDA tools like DesignCompiler/Genus, Primetime/PrimePower, ICC2/Innovus, Redhawk/Voltus
  • Bachelors Degree or equivalent (12 years) work experience (If an, Associates Degree with 6 years of work experience)

Bonus points if:

  • Experience running power analysis in vector and vector-less modes and achieving optimal QoR on low power designs.
  • Knowledge of static timing analysis, power analysis and concepts, defining timing and power constraints exceptions, switching activity definitions and simulation vectors
  • Experience with power integrity analysis at block level or top level, including EM, IR & ESD analysis, power reduction techniques in SOC design.

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