Hardware Engineer

3 weeks ago

Town of Poland, United States MA CAPITAL U.S. LLC Full time

MA Capital is a proprietary trading firm specializing in systematic and high‑performing discretionary strategies across multiple asset classes. We leverage advanced technology, quantitative research, and sophisticated models to capitalize on opportunities in global markets. Our culture is built on innovation, efficiency, and transparency. We are committed to providing liquidity and supporting fair, efficient markets, while ensuring our traders and professionals have flexibility, tools, and continuous learning opportunities to succeed. Position Overview We are seeking a skilled mid‑to‑senior‑level FPGA engineer for a 1‑month contract to build a SystemVerilog‑based HLS wrapper using the ExaNIC FDK TCP offload framework. The engineer will design adapter‑agnostic interfaces, CDC/FIFO modules between 10G network and PCIe clock domains, and host integration via the ExaNIC FDK driver and C API. Target latency is under 100 ns with line‑rate performance. Key Responsibilities Develop SystemVerilog HLS wrapper and card‑agnostic interfaces. Bridge AXI4‑Stream ↔ Avalon‑ST protocols with robust flow control. Use ExaNIC FDK driver and C API for host ↔ card data/control. Build testbench with SVA and functional coverage. Produce performance analysis and optimization report. Required Qualifications AXI4‑Stream and Avalon‑ST design and optimization. PCIe integration and driver‑based communication. Strong C/C++ programming with hardware drivers. SystemVerilog with advanced constructs (interfaces, packages, assertions). Vivado HLS 2020.1 for C/C++ → RTL synthesis and optimization. Vivado 2025.1 automation, CDC/FIFO macros, and Tcl scripting. RTL simulation and waveform‑driven debug. Technical Environment Primary Language: SystemVerilog Framework: ExaNIC FDK with TCP offload Protocols: AXI4‑Stream and Avalon‑ST Host Communication: ExaNIC FDK driver and C API Target Latency:

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