Design Verification Engineer
4 weeks ago
Pay found in job post: Retrieved from the description. $310,000.00/yr - $380,000.00/yr About The Team OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co‑design hardware tightly integrated with AI models. In addition to delivering production‑grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI. About The Role OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting‑edge ML accelerators. You will play a key role in verifying complex hardware systems—ranging from individual IP blocks to subsystems and full SoC—working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale. Key Responsibilities Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full‑chip SoC‑level functionality. Define verification plans based on architecture and microarchitecture specs. Develop constrained‑random, directed, and system‑level testbenches using SystemVerilog/UVM or equivalent methodologies. Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness. Drive bug triage, root cause analysis, and work closely with design teams on resolution. Contribute to regression infrastructure, coverage analysis, and closure for both block‑ and top‑level environments. Qualifications BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification. Proven success verifying complex IP or SoC designs in industry‑standard flows. Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi). Strong knowledge of computer architecture concepts, memory and cache systems, coherency, interconnects, and/or ML compute primitives. Familiarity with performance modeling, formal verification, or emulation is a plus. Experience working in fast‑paced, cross‑disciplinary teams with a passion for building reliable hardware. To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations. About OpenAI OpenAI is an AI research and deployment company dedicated to ensuring that general‑purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity. We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic. For additional information, please see OpenAI’s Aff ~» ] ... #J-18808-Ljbffr
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Design Verification Engineer
2 weeks ago
San Francisco, CA, United States Eximietas Design Full timeEximietas Design is a leading technology consulting and solutions development firm specializing in VLSI, Cloud Computing, Cyber Security, and AI/ML. Our engineering leadership team brings decades of experience from top-tier semiconductor and technology companies. With a deep commitment to innovation and excellence, we deliver cuttingedge solutions that help...
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Design Verification Engineer
3 weeks ago
San Francisco, United States Eridu AI Full timeJoin to apply for the Design Verification Engineer role at Eridu AIJoin to apply for the Design Verification Engineer role at Eridu AIGet AI-powered advice on this job and more exclusive features.This range is provided by Eridu AI. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.Base pay...
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Design Verification Engineer
5 days ago
San Francisco, California, United States Chiparama Full timeJob Title:Design Verification Engineer (High Priority Requirement)Location:San Francisco Bay AreaEmployment Type:ContractAbout the RoleWe are looking for a motivated Design Verification Engineer to join our team on a high-priority requirement. The role involves developing test plans, creating verification environments, and ensuring functional correctness of...
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Design Verification Engineer
4 weeks ago
San Francisco, United States EDA CAREERS, (Technology Futures Inc). Full timeGet AI-powered advice on this job and more exclusive features.Direct message the job poster from EDA CAREERS, (Technology Futures Inc).President at EDA-CAREERS and TECHNOLOGY FUTURES Inc.YOU MUST HAVE WORKING KNOWLEDGE OF EDA tools and Semiconductors!PLEASE HAVE EDA/SEMICONDUCTOR EXPERIENCE WHEN APPLYING!My client is a promising, innovative, well-funded...
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Design Verification Engineer
2 days ago
San Francisco, California, United States Amadeus Search Full timeTitle: Design Verification Engineer – Internal IPLocation: Bay Area (hybrid) or TorontoAbout the Company:A fast-growing AI startup designing next-generation compute hardware. The company specializes in building high-performance IP blocks and accelerators, aiming to enable leading‐edge AI workloads with custom silicon and software stacks.Role...
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Design Verification Engineer
2 days ago
San Francisco, California, United States Imparé Full timeImpare is on the hunt for ahigh-caliber Design Verification Engineerwho's ready to work on cutting-edge semiconductor projects with a global impact.We're specifically looking for:Expertise in DV (Design Verification)— UVM, SystemVerilog, and modern verification methodologies.Location Flexibility— Based inPakistan with a valid US visa, or acurrent...
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Design Verification Engineer
4 days ago
San Francisco, United States Eridu Full timeEridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. Today’s AI model performance is often gated by infrastructure bottlenecks. Eridu AI introduces multiple industry-first innovations across semiconductors, software and systems to deliver solutions that improves AI data center...
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Design Verification Engineer
3 days ago
San Francisco, CA, United States Kasmo Global Full timeTitle : Design Verification Engineer Location : San Jose, C s a Design Verification Engineer, you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Responsibilities Triage regression failures and make testbench updates Debug functional errors in RTL model using simulation and debug...
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Design Verification Engineer
1 week ago
San Francisco, CA, United States Kasmo Global Full timeTitle : Design Verification Engineer Location : San Jose, C s a Design Verification Engineer, you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Responsibilities Triage regression failures and make testbench updates Debug functional errors in RTL model using simulation and debug...
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Design Verification Engineer
7 days ago
San Francisco, CA, United States Kasmo Global Full timeTitle : Design Verification Engineer Location : San Jose, C s a Design Verification Engineer, you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Responsibilities Triage regression failures and make testbench updates Debug functional errors in RTL model using simulation and debug...
