RTL Design Engineer

1 month ago


san jose, United States Sintegra Inc. Full time

Position Summary:


Needed domains are NVMe and PCIe and desired experience having been involved in SSD controller design. The tasks are:


1 Debugging issues seen in the lab if they appear to be hardware related and the firmware team needs help. Debugging activities include but are not limited to:

  • 1 Analyzing the logs, examining registers, capturing PCIe traces, identifying issues at host or SSD PCIe ports.
  • 2 Interpreting debug information available in the chip - status registers, counters, interrupts, errors, and error-related information.
  • 3 Running simulations to understand the hardware behavior and/or to test failure mechanisms if required.
  • 4 Root-cause, identify the work-around, and guide the firmware team on register settings and sequence for the work-around. Identify ECO if required, with metal ECO always a priority


2 Assisting the firmware team to support their questions around hardware behavior and registers. Reviewing the RTL code and and registers to understand the behavior of both the code and registers.



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