Lead RTL Design Engineer, RISC-V
2 days ago
Lead RTL Design Engineer / RISC-V
We are seeking an experienced design engineer to lead development of complex IP subsystems based on the open-source RISC-V architecture. The right candidate will have deep technical expertise combined with exceptional leadership skills.
Responsibilities:
- Lead microarchitecture and RTL design of complex IP subsystems partnering with architecture teams.
- Support verification and physical design teams to deliver high quality subsystems meeting appropriate PPA targets.
- Mentor junior engineers to build a high performing team.
Minimum Qualifications:
- Bachelors or Masters degree in electrical, computer engineering or related field.
- BS+8 years or MS+6 years of industry experience successfully delivering complex IP subsystems.
Skills & Qualifications Required:
- Demonstrated experience in developing microarchitecture from the ground up for complex IP blocks and delivering high quality designs.
- Deep experience in RTL development in SystemVerilog/Verilog.
- Well versed in industry standard RTL quality check methodologies such as lint and CDC checks.
- Strong background in industry standards and protocols such as PCIe, Ethernet, CXL, AMBA AXI etc.,
- Demonstrated team leadership experience with outstanding communication skills.
- Highly motivated self-starter with strong execution mindset and collaborative approach.
- Post-silicon debug experience strongly preferred.
Please send a copy of your resume to jerald.baker@motektech.com
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