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Senior Synthesis Design Engineer
3 months ago
Xconn-technologies Inc is a Silicon Valley based company working on the world’s leading edge PCIe & CXL Switch. Xconn-technologies is seeking a highly motivated & Passionate Principal design engineer to lead its ASIC front to back activities for Synthesis, Prime time, design constraints development.
Job Description:
As an ASIC front to back design lead, you will lead the establishing & maintaining Synthesis, STA, Equivalency flows. You will be working with the ASIC design engineers to ensure high quality RTL, design constraints & Netlist preparation to hand off to a third-party physical design company. You will be responsible for ensuring the physical design partner receives Netlist & assist them with the design constraints issues as well as overseeing the floor planning, place & route & CDC placements. Once the Place & Route is complete, you will receive the post-layout Netlist to resolve the timing closure issues. PCIe/CXL switch chips have a high gate count & require a deep understanding of hierarchical Synthesis.
Responsibilities:
- Build flows for methodologies incorporating front to back flow for Lint, Synthesis, prime time timing analysis, CDC & equivalency check.
- Writing scripts & establishing automation for Synthesis & Prime time tools.
- Provide support for ASIC tools and flows
- Work with 3rd party vendor with the Netlist hand-off & oversee the physical design & ensure a clean tape out.
- Full chip & block level timing constraints ensuring area & timing optimization
- Implement functional ECOs
- Monitoring DFT insertion for scan, memory Bist & Loopback tests mechanisms.
Requirements:
- BS or MS in Electrical or Computer engineering.
- 10+ years of experience in chip development & familiarity with ASIC CAD & EDA tools
- Knowledge with Synopsys synthesis & STA tools.
- Experience with high gate count ASICs
- Experience with ASIC methodologies such as Verilog design, Lint, Synthesis, STA & DFT.
- Strong track record of hierarchical synthesis, STA, Lint, CDC & LEC methodologies,
- Strong experience in design constraints
- Solid experience in Hierarchical Synthesis & Static timing analysis.
- Proficiency in Perl scripting for automation.
