Principal Synthesis Engineer
1 week ago
Job Description:
As an ASIC front to back design lead, you will lead the establishing & maintaining Synthesis, STA, Equivalency flows. You will be working with the ASIC design engineers to ensure high quality RTL, design constraints & Netlist preparation to hand off to a third-party physical design company. You will be responsible for ensuring the physical design partner receives Netlist & assist them with the design constraints issues as well as overseeing the floor planning, place & route & CDC placements.
• Build flows for methodologies incorporating front to back flow for Lint, Synthesis, prime time timing analysis, CDC & equivalency check.
• Writing scripts & establishing automation for Synthesis & Prime time tools.
• Provide support for ASIC tools and flows
• Work with 3rd party vendor with the Netlist hand-off & oversee the physical design & ensure a clean tape out.
• Full chip & block level timing constraints ensuring area & timing optimization
• Implement functional ECOs
• Monitoring DFT insertion for scan, memory Bist & Loopback tests mechanisms.
Requirements:
• BS or MS in Electrical or Computer engineering.
• 10+ years of experience in chip development & familiarity with ASIC CAD & EDA tools • Knowledge with Synopsys synthesis & STA tools
. • Experience with high gate count ASICs
• Experience with ASIC methodologies such as Verilog design, Lint, Synthesis, STA & DFT.
• Strong track record of hierarchical synthesis, STA, Lint, CDC & LEC methodologies, • Strong experience in design constraints
• Solid experience in Hierarchical Synthesis & Static timing analysis.
• Proficiency in Perl scripting for automation
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