Field-Programmable Gate Arrays Engineer

Job DescriptionJob DescriptionWe are seeking a Gate Technician to join our team in Santa Barbara, California. Job Description:As a Gate Technician, you will be responsible for ensuring the proper functioning and maintenance of various gate systems. Your duties will include customer interaction, troubleshooting electrical components, welding repairs and...

We are seeking a Compiler Engineer to join our growing team. The Compiler Engineer will contribute to the design and implementation of an embedded machine learning (ML) system stack and TinyML applications to run on the world's most energy-efficient programmable processor. This position is a unique opportunity to develop applications for cutting-edge...

We are seeking a Compiler Engineer to join our growing team. The Compiler Engineer will contribute to the design and implementation of an embedded machine learning (ML) system stack and TinyML applications to run on the world’s most energy-efficient programmable processor. This position is a unique opportunity to develop applications for cutting-edge...

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high...

Job Title: Analog Layout EngineerJob Description & Skill Requirement: • 5- 10yrs Exp range engineers RequiredPort schematics from the previous project• Run pre-layout simulations and implement ECOs to meet design targetsa. Prepare and present Pre-Layout Design Review• Guide layout engineer to implement the layout• Run post-layout simulations and...

Job Title: Analog Layout EngineerJob Description & Skill Requirement: • 5- 10yrs Exp range engineers RequiredPort schematics from the previous project• Run pre-layout simulations and implement ECOs to meet design targetsa. Prepare and present Pre-Layout Design Review• Guide layout engineer to implement the layout• Run post-layout simulations and...

Job Title: Analog Layout EngineerJob Description & Skill Requirement: • 5- 10yrs Exp range engineers RequiredPort schematics from the previous project• Run pre-layout simulations and implement ECOs to meet design targetsa. Prepare and present Pre-Layout Design Review• Guide layout engineer to implement the layout• Run post-layout simulations and...

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high...

Position Responsibilities: Logic Design to support DFT features Automate DFT Flows (Scan, Compression & MBIST) used for complex multi-million gate SoC Verification of DFT Logic and analysis of fault coverage Timing analysis for DFT Modes   Minimum Requirements: MSEE in Electrical / Computer Engineering Knowledge of DFT fundamentals ...

Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix's FPGA and eFPGA IP offerings are further...

Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix's FPGA and eFPGA IP offerings are further...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...

Position Details: Title: Engineer in Charge (EIC) Location: Santa Clara, CA Shift: Day shift, typically M – F Compensation: $150K depending on experience and qualifications and annualized bonus. Benefits: Medical, dental, vision and 401K (see website for more information). Excellent professional and personal development opportunities in an international...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara. Make sure to apply quickly in order to maximise your chances of being considered for an interview Read the complete job description below. On going needs additional 10 engineers in team. Position detail: SOC verification Experience level : 5-20 years Architect block and full-chip...

Position Details:Title: Engineer in Charge (EIC)Location: Santa Clara, CAShift: Day shift, typically M – FCompensation: $150K depending on experience and qualifications and annualized bonus.Benefits: Medical, dental, vision and 401K (see website for more information). Excellent professional and personal development opportunities in an international...

Position Details:Title: Engineer in Charge (EIC)Location: Santa Clara, CAShift: Day shift, typically M – FCompensation: $150K depending on experience and qualifications and annualized bonus.Benefits: Medical, dental, vision and 401K (see website for more information). Excellent professional and personal development opportunities in an international...

Title: Sr Infrastructure Engineer. 100% Remote Role. We are seeking a skilled Systems Engineer Consultant to join our team to provide architectural governance and strategic guidance for the Microsoft Power Platform and Fabric environment. The ideal candidate will have a strong background in systems engineering with a specific focus on Microsoft technologies,...

FIP CMO is looking for a circuit design engineer to join our design team. Our team is responsible for developing Large Signal Arrays (custom multi-ported register file). Job function involves understanding and defining PV methodology, Pn. P projectio Design Engineer, Engineer, Design, Technology, Business Services