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Design Verification Engineer
2 months ago
Job Title: Verification engineer
Location: Menlo park CA
Duration: Contract
- Expert on the System Verilog and Advanced knowledge of HVL methodology (UVM)
- Must setup up the verification environment, Test bench development, test plan and coding from scratch.
- Define ASIC/SoC verification strategy
- Full chip TB Architecture definition
- UVM-based test bench development
- SV functional coverage, Assertions coding
- Test case development, coding, execution, bug analysis, and end-to-end ownership.
- Experience in Perl/Shell scripting
- Should Coordinate with design team counterparts in RTL design.
- Experience on any of the below protocols is an added advantage:
- DDR/LPDDR
