SI/ PI Engineer

Strong lab skills with measurement experience (VNA, TDR, Real Time/Sampling Scopes, BERT, SSA) Working experience with high speed NRZ and PAM4 Serdes, PLLs, retimer Understanding the Clock architecture Ability to troubleshoot and analyze complex problems, multi-task and meet deadlines. Knowledge of DDR3, DDR4 Self-motivated, self-directed, and a team...

Title: Hardware Engineer Location: San Diego, CA (Onsite) Job Type: Fulltime (USC & GC) Must need skills: Hardware, architecture, (HSIO or High Speed), Signal Integrity, PCB designer. - HW/architecture design side: one who can collate requirements and drive complex boards by defining power grid, system architecture and then preceding to schematics and...

What You’ll Do Semiconductor Packaging Engineers provide project management, package design/development and sustaining support for integrated circuit or semiconductor assemblies, various other electronic components and/or completed units. Mission of the Packaging Solutions Center is to find package solutions beyond Silicon to make next performance systems...

Must need skills: Hardware, architecture, (HSIO or High Speed), Signal Integrity, PCB designer - HW/architecture design side : one who can collate requirements and drive complex boards by defining power grid, system architecture and then preceding to schematics and ability to work with a PCB designer to drive the design, SI/PI etc. - He/she should also be...

Sanmina Corporation (Nasdaq: SANM) is a leading integrated manufacturing solutions provider serving the fastest-growing segments of the global Electronics Manufacturing Services (EMS) market.In this position, the engineer will lead the signal integrity (SI) measurements at the Sanmina PCB corporate SI lab for bare printed circuit boards (PCB) and assembled...

6 Months contract with possibility of extension Location - San Jose (Hybrid) Rate - $80 to $120 per hour Overview: Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for SoCs. Responsibilities: Strong understanding...

6 Months contract with possibility of extensionLocation - San Jose (Hybrid)Rate - $80 to $120 per hour Overview: Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for SoCs.Responsibilities:Strong understanding of...

6 Months contract with possibility of extensionLocation - San Jose (Hybrid)Rate - $80 to $120 per hour Overview: Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for SoCs.Responsibilities:Strong understanding of...

Physical Design STA EngineerLocation:- San Jose, CA (Hybrid Schedule)Duration:- 6 MonthsPay rate:- $80 - $120/hr W2.Responsibilities of Physical Design STA EngineerPerform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for...

Job DescriptionJob DescriptionPhysical Design STA EngineerLocation:- San Jose, CA (Hybrid Schedule)Duration:- 6 MonthsPay rate:- $80 - $120/hr W2.Responsibilities of Physical Design STA EngineerPerform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise...

Physical Design STA EngineerLocation:- San Jose, CA (Hybrid Schedule)Duration:- 6 MonthsPay rate:- $80 - $120/hr W2.Responsibilities of Physical Design STA EngineerPerform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for...

Physical Design STA EngineerLocation:- San Jose, CA (Hybrid Schedule)Duration:- 6 MonthsPay rate:- $80 - $120/hr W2.Responsibilities of Physical Design STA EngineerPerform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for...

Job Description In this highly visible role as Senior Hardware Engineer, you will Drive product from concept to production Lead system design on embedded computing system products Create hardware specs and develop test plans Capture Schematics using Orcad Work with Layout, Mechanical and SI engineers to complete the designs Bring up systems and...

Work with Architects, Chip Leads, and Customers on SOC IP design, development, timing closure, power analysis, methodology alignment, and program execution to ensure pre-silicon and post silicon targets are met. Integrating, evolving, and optimizing IP blocks across a range of products and use cases for SoCs in driving, 5G, cloud and gaming and other...

STA Physical Design Engineer LOCATION: San Jose, CA (hybrid 3 days onsite) DURATION: 6+ Months Description: Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for SoCs. - Strong understanding of digital design...

Who We Are The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco...

STA Physical Design EngineerLOCATION: San Jose, CA (hybrid 3 days onsite)DURATION: 6+ MonthsDescription:Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for SoCs.- Strong understanding of digital design concepts,...

STA Physical Design EngineerLOCATION: San Jose, CA (hybrid 3 days onsite)DURATION: 6+ MonthsDescription:Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for SoCs.- Strong understanding of digital design concepts,...

STA Physical Design EngineerLOCATION: San Jose, CA (hybrid 3 days onsite)DURATION: 6+ MonthsDescription:Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for SoCs.- Strong understanding of digital design concepts,...

Links Technology Solutions is currently seeking an experienced Mechanical Engineering Technical Lead to fill an opening with an Information Technology company. Responsibilities of the Mechanical Engineering Technical Lead Design and deliver next generation chassis and cards that meets system product requirements. Perform detailed 2D tolerance analysis for...