Current jobs related to RTL Design Engineer - Santa Clara - LanceSoft, Inc.
-
RTL Design Engineer
4 weeks ago
Santa Clara, California, United States Capgemini Engineering Full timeJob Description:We are seeking a highly skilled RTL Engineer to join our team at Capgemini Engineering. As an RTL Engineer, you will play a critical role in ensuring the quality and reliability of our digital designs.Key Responsibilities:Setup and run tools like LINT, CDC, RDC, and X-propagation at both block and chip levels.Work closely with the design team...
-
RTL Design Engineer
1 month ago
Santa Clara, California, United States Capgemini Full timeJob Description:We are seeking a highly skilled RTL Engineer to join our team at Capgemini Engineering. As a key member of our design team, you will be responsible for setting up and running tools like LINT, CDC, RDC, and X-propagation at both block and chip levels.You will work closely with our design team to consistently improve RTL quality and ensure it...
-
RTL Design Engineer
4 weeks ago
Santa Clara, California, United States Capgemini Full timeJob Description:We are seeking a highly skilled RTL Engineer to join our team at Capgemini Engineering. As a key member of our design team, you will be responsible for setting up and running tools like LINT, CDC, RDC, and X-propagation at both block and chip levels.You will work closely with our design team to consistently improve RTL quality and ensure it...
-
RTL Design Engineer
1 month ago
Santa Clara, California, United States Capgemini Engineering Full timeJob Description:We are seeking a highly skilled RTL Engineer to join our team at Capgemini Engineering. As an RTL Engineer, you will play a critical role in setting up and running tools like LINT, CDC, RDC, and X-propagation at both block and chip levels. You will work closely with the design team to consistently improve RTL quality and ensure it is ready...
-
ASIC/RTL Design Engineer
3 weeks ago
Santa Clara, United States Experis Full timeOur client in the technology industry is seeking an ASIC/RTL Design Engineer to join their team. As an ASIC/RTL Design Engineer, you will be part of the design team supporting the development of required features. The ideal candidate will have a good understanding of SystemVerilog, analyzing existing designs and making modifications, able to understand tools...
-
ASIC/RTL Design Engineer
3 weeks ago
Santa Clara, United States Experis Full timeOur client in the technology industry is seeking an ASIC/RTL Design Engineer to join their team. As an ASIC/RTL Design Engineer, you will be part of the design team supporting the development of required features. The ideal candidate will have a good understanding of SystemVerilog, analyzing existing designs and making modifications, able to understand tools...
-
RTL Engineer
2 weeks ago
Santa Clara, California, United States Capgemini Engineering Full timeJob Description:We are seeking a highly skilled RTL Engineer to join our team at Capgemini Engineering. As a key member of our design team, you will be responsible for setting up and running tools like LINT, CDC, RDC, and X-propagation at both block and chip levels. Your primary goal will be to consistently improve RTL quality and ensure it is ready for...
-
RTL Engineer
4 weeks ago
Santa Clara, California, United States Capgemini Engineering Full timeAbout the RoleCapgemini Engineering is seeking a skilled RTL Engineer to join our team. As an RTL Engineer, you will be responsible for designing and verifying digital circuits using Verilog and SystemVerilog. You will work closely with the design team to ensure that the digital circuits meet the required specifications and are ready for synthesis and...
-
RTL Engineer
4 weeks ago
Santa Clara, California, United States Capgemini Full timeJob Description:We are seeking a highly skilled RTL Engineer to join our team at Capgemini Engineering. As a key member of our design team, you will be responsible for setting up and running tools like LINT, CDC, RDC, and X-propagation at both block and chip levels.You will work closely with our design team to consistently improve RTL quality and ensure it...
-
Senior RTL Design Engineer
1 month ago
Santa Clara, California, United States SiFive Full timeAbout SiFiveSiFive is a pioneering company that introduced RISC-V to the world, revolutionizing the future of compute by bringing the limitless potential of RISC-V to high-performance and data-intensive applications.Our compute platforms are enabling leading technology companies to innovate, optimize, and deliver advanced solutions across every market...
-
Senior RTL Design Engineer
3 days ago
Santa Clara, California, United States SiFive Full timeAbout SiFiveSiFive is a pioneering company that introduced RISC-V to the world, revolutionizing the future of compute. Our mission is to bring the limitless potential of RISC-V to the highest performance and most data-intensive applications. We are committed to enabling leading technology companies to innovate, optimize, and deliver the most advanced...
-
RTL Analysis Methodology Engineer
2 weeks ago
Santa Clara, California, United States Yoh - A Day & Zimmerman Company Full timeJob Title: RTL Analysis Methodology EngineerWe are seeking an experienced RTL Analysis Methodology Engineer to join our AI core design and verification team. The successful candidate will be responsible for designing and implementing scalable RTL analysis methodologies, integrating EDA tools and scripts for automation of RTL analysis workflows, and...
-
RTL Analysis Methodology Engineer
2 weeks ago
Santa Clara, California, United States Yoh - A Day & Zimmerman Company Full timeRTL Analysis Methodology EngineerWe are seeking a highly skilled RTL Analysis Methodology Engineer to join our AI core design and verification team. The successful candidate will be responsible for developing and implementing scalable RTL analysis methodologies, integrating EDA tools and scripts for automation of RTL analysis workflows, and conducting...
-
RTL Analysis Methodology Engineer
2 weeks ago
Santa Clara, California, United States Yoh - A Day & Zimmerman Company Full timeRTL Analysis Methodology EngineerWe are seeking a highly skilled RTL Analysis Methodology Engineer to join our AI core design and verification team. The ideal candidate will have strong experience in RTL design, EDA tools, and automation.Key Responsibilities:Design and implement scalable RTL analysis methodologies for areas such as linting, CDC, RDC, and...
-
RTL Analysis Methodology Engineer
2 weeks ago
Santa Clara, California, United States Yoh - A Day & Zimmerman Company Full timeRTL Analysis Methodology EngineerWe are seeking a highly skilled RTL Analysis Methodology Engineer to join our AI core design and verification team. The ideal candidate will have strong experience in RTL design, EDA tools, and git/Ci enablement.Key Responsibilities:Design and implement scalable RTL analysis methodologies for areas such as linting, CDC, RDC,...
-
RTL Analysis Methodology Engineer
3 weeks ago
Santa Clara, United States Yoh - A Day & Zimmerman Company Full timeRTL Analysis Methodology Engineer Looking for an RTL Analysis Methodology Engineer to join an AI core design & verification team. This team is focused on architecting, developing, & verifying a new AI core. This new core is architected to support modern AI workloads for both inference & training use cases. The general purpose architecture is also used in...
-
Senior RTL Design Engineer
1 month ago
Santa Clara, California, United States SiFive Full timeAbout SiFiveSiFive is a pioneering company that introduced RISC-V to the world, revolutionizing the future of compute by bringing the limitless potential of RISC-V to high-performance and data-intensive applications.Our compute platforms are enabling leading technology companies to innovate, optimize, and deliver advanced solutions across every market...
-
Server SOC RTL Design and Integration Engineer
4 weeks ago
Santa Clara, California, United States cis-ieee Full timeJob DescriptionWe are seeking a highly skilled Server SOC RTL Design and Integration Engineer to join our team. As a key member of our Design Engineering Group, you will be responsible for designing and integrating complex System on a Chip (SoC) architectures.ResponsibilitiesDefine and design SoC architectures, including logic design and system...
-
Senior RTL Design Engineer
3 days ago
Santa Clara, California, United States SiFive Full timeAbout SiFiveSiFive is a pioneering company that introduced RISC-V to the world, transforming the future of compute by bringing the limitless potential of RISC-V to high-performance and data-intensive applications. Our unrivaled compute platforms enable leading technology companies to innovate, optimize, and deliver advanced solutions across various market...
-
ASIC/RTL Design Engineer
2 weeks ago
Santa Clara, CA, United States Experis Full timeOur client in the technology industry is seeking an ASIC/RTL Design Engineer to join their team. As an ASIC/RTL Design Engineer, you will be part of the design team supporting the development of required features. The ideal candidate will have a good understanding of SystemVerilog, analyzing existing designs and making modifications, able to understand tools...
RTL Design Engineer
4 months ago
KEY RESPONSIBILITIES:
• Microarchitecture development of IP subsystems
• Perform RTL design of digital components.
• Work with functional verification team to meet coverage and quality standards.
• Analyze/fix Lint and CDC errors of the components.
• Guarantee quality/timely deliverables meeting project’s schedule.
• Help to improve/automate design process.
• Support post-silicon product bring-up/debug.
PREFERRED EXPERIENCE:
• 10 years' experience in RTL coding
• Knowledge of PCIe Gen5 and PIPE specification
• Knowledge of ASIC development flows
• Knowledge of system verilog
• Multi-clock domain designs.
• Design constraints for synthesis and static timing analysis.
• Knowledge of AXI/AMBA protocol
• Knowledge of front-end RTL design tools and methodologies.
• Knowledge of front-end requirements and deliverables for verification, validation, physical design, architecture, security, dfx, power.
o Verification - coverage, testplan, debug
o Physical design – timing, clock crossings, reset crossings, ECOs (manual, formal)
• Ability to work and effectively collaborate with partners
• Experience with rtl simulation tools, rtl linting tools, reset domain crossings, clock domain crossings, synthesis, RAM generation (area, timing, power, SEU tradeoffs),
• Knowledge of scripting languages like Perl, tcl or cshell
EDUCATION:
• Bachelor's or Master's in Computer Engineering