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Senior DFT Engineer

2 months ago

Austin, United States MediaTek Full time

Job Description

  • Responsible for Design for Test (DFT) of high performance (>1GHz) CPU subsystems using latest DFT methodologies/techniques.
  • Define and implement DFT architecture to enable all the test coverage goals are met.
  • Responsible for generating test pattern and simulating them in Gate Level simulations.
  • Generate and debug failing patterns on Silicon.


Required Skills

  • 4+ Years of hands on experience in Design for Test (DFT) of high speed (>1GHz) Complex IP, CPU Subsystems and/or SoC
  • Experienced in latest DFT methodologies for High Speed (>1GHz) designs : Scan insertion, Scan compression, ATPG pattern generation, At-Speed testing
  • Experienced in defining and deploying DFT architecture for complex designs preferably CPU subsystems or SoCs to meet the test coverage goals
  • Expert at using industry standard DFT tools, preferably Synopsys DFT compiler and Tetramax
  • Proven Ability to simulate and debug DFT patterns using Gate Level Simulations (GLS)
  • Experience in running and debugging DFT patterns during Silicon Bringup
  • Excellent communication skills and ability to communicate and work with other world-wide sites


Preferred Skills

  • Experience with Memory BIST (MBIST) and Logic BIST
  • Proven ability to develop and deploy new DFT methodologies.
  • Strong scripting skills using Perl or Tcl
  • Knowledge of JTAG