Custom Circuit Methodology Engineer

2 months ago

Austin, Texas, United States Apple Full time
Summary

Posted: Feb 20, 2024

Role Number:


Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. The people who work here have reinvented entire industries with Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices - strengthening our dedication to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple products. Multifaceted, smart people and inspiring, cutting-edge technologies are the norm here. As a member of the Mixed-Signal design team, you will build and support innovative design methodology, and customize and automate flows for sophisticated mixed-signal IP designs. The design flows are used by multiple different IPs of multiple projects at multiple sites. You will collaborate with mixed signal design teams, CAD teams, and EDA vendors. Good interpersonal skill is essential. Excellent verbal and written communication in English is required.

Description

As a member of the custom methodology team, you will be involved in all the aspects of the custom design process, from schematic capture, layout, extraction to simulation and EMIR/ timing analysis flows. Your responsibilities include but are not limited to the following: Work with design and CAD teams to identify inefficiencies in the mixed-signal design process and drive the improvement efforts to completion. Prototype and develop innovative solutions to address the design teams' needs. Work with the CAD team to debug issues and enhance existing flows. Test, deploy and support new and existing tools and flows. Provide documentation and training to design teams.

Key Qualifications
  • Understanding of SPICE simulation, Cadence ADE environment, Xcelium and/or VCS CoSim is required
  • Proficiency in multiple programming languages (Perl, Python, SKILL, TCL/TK, Unix Shell).
  • Experience in Circuit Check and STA/NanoTime analysis is a plus.
  • Experience in flow development and automation in a rapid design environment.
  • Exposure to Cadence Virtuoso Framework, Schematic Editor and Layout tools, VXL and CDFs is a plus
  • Strong interpersonal/communication skills and ability to work with cross functional teams.
  • Preferred 3+ years of relevant industry experience.
Education & Experience

BS degree in technical discipline with minimum 3 years of relevant experience. Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.

Additional Requirements

More
  • Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.

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