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Physical Design Engineer

4 months ago

Santa Clara, California, United States QData Full time

Job DescriptionSynthesis using DC Expert in Synthesis to Tape-out flow including Layout DFT Timing Closure and Chip FinishingFloorplan P&R Ability to independently handle complex blocks to closure right from SynthesisPhysical verification (DRC LVS) Worked on at least 2 end to end projects those spanned across entire life cycle of developmentSTA & Timing closure Ability to communicate with architecture RTL design and other remote teamsLayout clean-up Preferably experience in 20 nm 14 nm flows Performing a wide range of back-end activities including synthesis of RTL DFT insertion power optimization Floor-planning PnR (Place and Route) Clock Tree Synthesis (CTS) Timing closure (STA) DRC LVS Antenna checks IR drop (RedHawk) multi voltage checks etc.

Participating in the development of a back-end SoC design flow. Experience of UPF low power design through synthesis place and route. Expertise in Synopsys suite (IC Compiler Primetime Design Compiler)Expericence 3-8 Years