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Power Integrity Engineer, Principal
1 month ago
In the System Solutions Group we are shaping solutions for dependable systems, requiring safety, security, reliability, low power and more. Our team works with customers and industry partners to understand their needs and identify technical requirements. We are passionate about methodologies and automation: we collaborate with customers to make their job easier when they develop their products.
Power Integrity Engineer, Principal
We’re looking for a 3DIC Packaging design engineer with emphasis on EMIR simulations.
In this role, you will be a part of a team that designs cutting edge packaging solutions for industry’s leading 3DIC customers in the datacenter, AI/ML space. You will architect the power delivery for the system including the multi-chip module, substrate, PCB and on-die PDN models. An in-depth understanding of PDN fundamentals is required to successfully architect PDN budgets and plans for modeling of multiple power domains on the silicon interposers and between chiplets.
We’re looking for an expert on setting up test-benches and running frequency and transient simulations and have expertise to design for low noise/spur, SSN and PSiJ. It is important to know how power delivery impacts PLLs, clocks and overall system jitter. You’ll work cross functionally with Synopsys’ IP teams to translate the industry’s largest IP portfolio of memory and SerDes IP’s electrical specifications into design requirements. The ideal candidate should be self-motivated, detail-oriented, and have strong coordination and partnership skills.
Qualifications
Bachelors, MS or Ph.D. degree in Electrical Engineering.10+ years of experience in Power Integrity fieldStrong knowledge of Power/Signal Integrity fundamentals (PDN, EMIR, Basic Analog circuits, Transmission Line theory, Xtalk, S-parameters, channel simulations)Experience with chip-level PDN analysis using Redhawk for EM-IR (both static and Dynamic), generated CPM models, etc…Expertise in the Electromagnetics field with 5+ years of hands-on experience using 2.5D and 3DFEM solvers such as SiWave and HFSS. System-level power integrity simulation: VRM + PCB + PKG + Interposer + Stacked dies. Has used tools like SiWave to extract PCB/Pkg models and optimized decoupling capacitors. Has run both frequency and time domain simulations to analyze impedance and ripple.In addition to the mentioned qualifications, candidates with a demonstrated ability to devise innovative design solutions will be highly valued.
Preferred ExperiencePerformed SI/PI simulations for HBM2+, UCIe and other chiplet and silicon interposer interfaces.Experience with 2/2.5D and/or 3D integration chip design projectsUnderstand ESD design and ran simulations using tools like Pathfinder to check for ESD sign-off at die + package.Through understanding of digital and analog equalization techniques such as CTLE, FIR, DFE, FFE and be able to use AMI models to setup channel simulations and be able to analyze the results to improve channel routings.The ideal candidate should have evidence of strong organizational and planning skills for engineering projects and possess good communication and presentation skills for executive project coordination.The candidate should also have experience working with multiple function teams for EDA tool collaboration.
The base salary range across the U.S. for this role is between $159,000 to $239,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on several job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
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