RTL Design Engineer

ASIC/RTL Design Engineer Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural...

Position Title: RTL Design Engineer Position Description: Protingent Staffing has an exciting contract opportunity for RTL Design Engineer with our client located in San Jose, CA.Project Description: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write...

RTL Design Engineer - Specialized (US) Location: San Jose, CA 95124 Onsite 12 Months Contract Job Description: Location: Onsite San Jose, CA JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and...

RTL Design Engineer - Specialized (US)Location: San Jose, CA 95124 Onsite 12 Months Contract Job Description: Location: Onsite San Jose, CA JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified...

Location: Onsite San Jose, CA JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for linting and simulation of design. Work with synthesis and backend teams for physical...

Location: Onsite San Jose, CA JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for linting and simulation of design. Work with synthesis and backend teams for physical...

Location: Onsite San Jose, CA JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for linting and simulation of design. Work with synthesis and backend teams for physical...

RTL Design Engineer - Specialized (US) Location: San Jose, CA 95124 Onsite 12 Months ContractJob Description: Location: Onsite San Jose, CA JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified...

Location: Onsite San Jose, CA JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for linting and simulation of design. Work with synthesis and backend teams for physical...

RTL ASIC Design Engineers with 8 to 15+ years of experience. No of Openings: 2 Sunnyvale, CA Job Description: 8+ years of Exp with Logic design /micro-architecture / RTL coding is a must. Expertise in Verilog & System Verilog is a must. Experience in Synthesis / Understanding of timing concepts for ASIC is required. Experience in design of DDR / USB...

Duration: 12 months contract Employment Type: W-2 Job Description: Microarchitecture development of IP subsystems Perform RTL design of digital components. Work with functional verification team to meet coverage and quality standards. Analyze/fix Lint and CDC errors of the components. Guarantee quality/timely deliverables meeting projects schedule. ...

Droisys is an innovation technology company focused on helping companies accelerate their digital initiatives from strategy and planning through execution. We leverage deep technical expertise, Agile methodologies, and data-driven intelligence to modernize systems of engagement and simplify human/tech interaction. Amazing things happen when we work in...

Physical Design Engineer (8-15 Years Experience) Work Location Santa Clara CA USA Customer: TechMahindra Job Description: As a Physical Design Engineer, you will play a crucial role in the RTL to GDS flow, including Synthesis and Place & Route (PNR). You will utilize tools such as Fusion Compiler and Cadence Innovus to optimize designs for...

ASIC/RTL Design Engineer - Senior (US) San Jose, CA 95124 3 days Onsite 12 Months Contract HM Notes: This is general SOC Design Engineer role. RTL Integration, coding exp required. Understanding interface of IP blocks required Documentation exp Verilog and system Verilog exp will be plus Verification exp will be plus but not...

Senior ASIC Design Engineer page is loaded Senior ASIC Design Engineer Apply locations US, CA, Santa Clara time type Full time posted on Posted 5 Days Ago job requisition id JR1967995 NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world’s leading SoC's and GPU's. This position offers the opportunity to have a...

Job DescriptionJob DescriptionPosition: Senior Silicon Design Engineer Location: Santa Clara, CA 95054 Duration: 6 Months (can be extended) Job Type: Contract Work Type: Onsite Job Description This is a Physical Design Engineering role that will require to take the design from RTL to GDS with synthesis, Place n Route, timing, and Physical Verification THE...

Job DescriptionJob DescriptionResponsibilities:As a Senior Logic Design Engineer, you will be responsible for:Developing micro-architecture specification of the logic circuit from reading and comprehending the Product Requirement Document (PRD)Developing the Register Transfer Level (RTL) design from the micro-architecture specification using Verilog or...

Job DescriptionJob DescriptionResponsibilities:As a Senior Logic Design Engineer, you will be responsible for:Developing micro-architecture specification of the logic circuit from reading and comprehending the Product Requirement Document (PRD)Developing the Register Transfer Level (RTL) design from the micro-architecture specification using Verilog or...

Front-End ASIC Lead Design Engineer - Santa Clara, CA Unique opportunity to join an established international company in their US expansion. Working from the US headquarters, you will have the ability to be an impact player working with other exceptionally talented people. The Front-End ASIC Design Engineer will be a key person in this growing design...

JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and internal IPs. Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC design...