uvm verification jobs in Chicago

As a Verification Engineer at IMC, you will be part of the R&D team. You'll have the opportunity to work on novel solutions to accelerate trading decisions to the technological limit. In addition, you'll work on forward looking solutions that anticipate future requirements.Your Core Responsibilities: Work in a small and globally distributed team that takes...

We are deploying machine learning directly onto custom hardware - and we want you to help drive it from the ground up. This is an initiative where you'll have the rare opportunity to architect solutions from scratch, influence technical research direction, and see your work drive real impact in one of the most demanding computing environments in the world.We...

A leading global trading firm is expanding its machine learning capabilities and looking for an experienced Hardware Machine Learning Engineer to help deploy ML directly onto custom hardware.This firm builds its own hardware, software, and infrastructure in-house, so when a model hits a latency wall or a resource ceiling, the engineer doesn't file a ticket...

Job Description: Verification Engineer Location: Chicago, IL - Onsite Duration: 6 to 8 months • Must have very good System Verilog/UVM experience in developing test benches • Must have experience with developing test benches with RISC-V based SoC • RISC-V processor verification is an added advantage ...

We are seeking a Design Verification Engineer to ensure the functional correctness, performance, and reliability of complex semiconductor designs such as ASICs, SoCs, GPUs, or CPUs. The role focuses on developing robust verification environments and validating RTL designs prior to tape-out. Key Responsibilities Develop and execute functional verification...

A semiconductor design company based in Chicago is seeking a Design Verification Engineer to ensure the functional correctness and reliability of complex semiconductor designs. Responsibilities include developing verification plans, building verification environments using SystemVerilog/UVM, and performing RTL debugging. The ideal candidate holds a relevant...

About the Role: Design Verification Engineer We are seeking a detail-oriented Design Verification Engineer to manage and oversee the daily operations of our ASIC/SoC verification workflows and testbench architecture. In this role, you will act as the vital link between our RTL design teams, system architects, and EDA tool vendors, ensuring that all hardware...