uci inc

Synopsys Inc in Hillsboro, Oregon seeks an experienced post-silicon validation engineer for UCIe die-to-die interface IP. You will own test plans, silicon sign-off, and drive lab automation across Python, C, and C++.You will lead complex debug spanning circuit design, package channels, and training firmware, mentor engineers, and deliver credible silicon...

Synopsys, Inc. seeks a seasoned engineering manager to lead a team of validation and characterization engineers focused on UCIe die‑to‑die interface IP. You will own end‑to‑end silicon characterization, drive sign‑offs, and manage lab budgets and staffing, balancing multiple programs and customer commitments. You will lead with hands‑on technical...

Synopsys Inc. is seeking an experienced Applications Engineer to drive UCIe IP integration in SoC flows for AI-enabled designs. You will guide customers through simulation, synthesis, floorplanning, and validation, working across design teams to resolve complex challenges.You will partner with R&D to develop deployment methodologies, influence product...

Synopsys Inc in Hillsboro, OR seeks a senior validation engineer to define and lead post-silicon validation for UCIe die-to-die IP. You will own the validation software stack in Python, coordinate lab bring-up, and drive cross-functional programs spanning design, firmware, and applications.Ideal candidates have 10+ years in high-speed mixed-signal...

Synopsys Inc. is seeking a highly experienced digital design engineer to lead RTL and PHY architecture for high-speed interfaces such as DDRIO and UCIe.You will own ASIC design cycles from concept to implementation, mentor engineers, and collaborate with verification, physical design, and system teams to deliver scalable silicon solutions. You will influence...

Synopsys, Inc. is seeking an experienced Applications Engineer to guide customers in integrating UCIe IP into SoCs and systems. You will lead technical engagements, validate integration, and partner with R&D to improve deployment methodologies while traveling as needed. You bring deep technical credibility, strong customer instincts, and the ability to drive...

Synopsys Inc. is seeking a skilled post-silicon validation engineer to own UCIe die-to-die interface IP validation, create lab automation software, and lead complex debugging across design, packaging, and protocol layers. You will also support customer bring-up and develop characterization methods for challenging die-to-die links, while mentoring peers. The...

Synopsys, Inc. is seeking a senior post-silicon validation engineer to own the die-to-die IP verification for UCIe interfaces.You will lead the evaluation and sign-off of silicon readiness, coordinating across analog, digital, and packaging teams to resolve complex issues. You will develop and maintain validation frameworks in Python, manage lab automation,...

Synopsys, Inc. seeks a seasoned engineering manager to lead a team of validation and characterization engineers focused on UCIe die‑to‑die interface IP. You will own end‑to‑end silicon characterization, drive sign‑offs, and manage lab budgets and staffing, balancing multiple programs and customer commitments.You will lead with hands‑on technical...

Synopsys, Inc. is seeking an experienced ASIC Digital Architect to drive the future of semiconductor technology in Austin. You will define and lead RTL design and verification at chip and block levels, shaping architectures for DDR, PCIe, CXL, UAL, and UCIe IO protocols while mentoring junior engineers.You will collaborate with cross-functional teams to...

Synopsys Inc is seeking an experienced ASIC Digital Architect to define and drive RTL design and verification at both chip and block levels. You will create design plans for DDR, PCIe, CXL, UAL, and UCIe IO protocols and work with cross-functional teams to ensure seamless integration and high-quality results.You will mentor junior engineers, promote best...

Synopsys, Inc. is seeking an experienced ASIC Digital Architect to drive the future of semiconductor technology in Austin. You will define and lead RTL design and verification at chip and block levels, shaping architectures for DDR, PCIe, CXL, UAL, and UCIe IO protocols while mentoring junior engineers. You will collaborate with cross-functional teams to...

Position: Design Verification Engineer (eInfochips Inc) Job Description: What You'll Be Doing: Strong SV/UVM expertise AXI/NOC/Ethernet/PCIe/UCIe Switch expertise is needed CPU ARM/RISC-V with C knowledge Regression & Coverage Closure What We Are Looking For: Responsible for architecting Verification Environment for ASIC SoC and providing...

Synopsys Inc in Hillsboro, OR seeks a senior validation engineer to define and lead post-silicon validation for UCIe die-to-die IP. You will own the validation software stack in Python, coordinate lab bring-up, and drive cross-functional programs spanning design, firmware, and applications. Ideal candidates have 10+ years in high-speed mixed-signal...

Synopsys, Inc. is seeking an experienced ASIC Digital Architect in Austin to lead RTL design and verification at chip and block levels.You will define design plans for complex digital designs and focus on high-speed IO protocols such as DDR, PCIe, UCIe, and Ethernet, collaborating with cross-functional teams to ensure integration and performance. You will...

Synopsys Inc. is seeking an experienced Applications Engineer to drive UCIe IP integration in SoC flows for AI-enabled designs. You will guide customers through simulation, synthesis, floorplanning, and validation, working across design teams to resolve complex challenges. You will partner with R&D to develop deployment methodologies, influence product...

Synopsys, Inc. is seeking an experienced RTL design leader to drive complex ASIC digital subsystems from concept to silicon. You will define architecture, translate requirements into clear specifications, and deliver high-quality RTL that is robust and scalable. You will work across design, verification, DFT and implementation, with experience in UCIe,...

Synopsys Inc in Sunnyvale invites an experienced Applications Engineer with deep expertise in Memory Interface IP to lead customer engagements, assist with integration and bring-up of DDR, LPDDR, HBM, and related controllers, and serve as a trusted technical advisor. You will work across engineering teams, deliver technical presentations, contribute to...

Cadence Design Systems, Inc. in San Jose seeks a seasoned Design Engineering Architect for Systems and Interfaces to drive IP integration and system-level design across customer engagements.You will shape reference designs, deliver advanced technical guidance, and lead cross-functional teams in pre- and post-sales activities. The role requires deep RTL...

TYLsemi, Inc. is seeking a Lead Performance Architect to drive architectural configuration, system-level simulation, and PPA optimization for chiplet integration including PCIe, UCIe, and NoC IPs.You will own trade-off analyses that determine what gets taped out and work with ESL tools to model full-chiplet behavior. Qualifications include 6+ years in...