eco logic

NVIDIA in Santa Clara, CA seeks a timing engineer to drive STA for DFT logic across GPUs/SoCs. You will collaborate with PD, DFX and Clocks teams to define constraints, ensure timing closure, and implement ECOs, while increasing automation and standardization.Required: BS or MS in Electrical/Computer Engineering with 2+ years (MS) or 5+ years (BS) of STA...

Role Number: 200634936Team: HardwareLocation: Santa ClaraPosted: 2025-12-04SummaryImagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and theres no telling what you could accomplish. Dynamic, hard-working people and...

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people.NVIDIA's world-leading hardware relies on design exploration beyond the limits of conventional tools. Our team develops highly optimized internal EDA...

We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip and off-chip interconnect network, MP coherency and last-level and system caches, focusing on such tasks as micro-architectural definition, RTL coding, logic debug, synthesis and timing closure, supporting...

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. NVIDIA's world-leading hardware relies on design exploration beyond the limits of conventional tools.Our team develops highly optimized internal EDA...

Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is...

We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip and off-chip interconnect network, MP coherency and last-level and system caches, focusing on such tasks as micro-architectural definition, RTL coding, logic debug, synthesis and timing closure, supporting...

Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is...

Role Number: Team: HardwareLocation: Santa ClaraPosted: SummaryImagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative...

We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip and off-chip interconnect network, MP coherency and last-level and system caches, focusing on such tasks as micro-architectural definition, RTL coding, logic debug, synthesis and timing closure, supporting...

To make electronics, you need chips, wafers, transistors, reticles, and... To make these, you must see, test and manufacture them at scale-faster and better than ever before. That's where KLA comes in. Whether you're early in your career or an experienced professional, you'll solve complex challenges, work alongside brilliant minds and help shape the future...

Role: VLSI Physical Designer Domain : VLSI Location - all over USA/ REMOTE   Physical Design: Provides services in transforming the RTL design into a physical layout of the chip using Synopsys Fusion Compiler synthesis and place-and-route tools. The physical design process involves specifying various constraints on the netlist, such as timing, power,...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. About The Team The Conformal team is a diverse group of innovative, talented, and passionate engineers committed to delivering cutting-edge verification technologies and trusted solutions to leading semiconductor and high-technology customers around...

Apple, Inc. is seeking a forward-thinking Physical Design Engineer in Cupertino to contribute to high-performance PHY design from RTL to GDSII. You will collaborate with architecture, CAD, timing and logic teams to deliver optimized PHY blocks and full-chip flows.The role emphasizes floor-planning, place & route, power-grid and clock specification...

Apple in Austin, TX, seeks a SOC Design and Integration Engineer to help design and integrate next‑generation, high‑performance, power‑efficient SoCs. You will write microarchitecture and design specs, implement and debug complex logic, and integrate IPs while supporting lint, CDC, synthesis, ECO, and front‑end integration; collaborate with SOC...

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers,...

NVIDIA Corporation seeks a Senior ASIC Physical Design Engineer, Netlisting, to drive high-frequency, low-power CPU/GPU/SoC design from block to full-chip level. You’ll handle netlist-related tasks, equivalence checking, and timing constraints while contributing to ECO implementation.Applicants should have 5+ years (BS) or 3+ years (MS) in...

Apple in Austin, TX, seeks a SOC Design and Integration Engineer to help design and integrate next‑generation, high‑performance, power‑efficient SoCs.You will write microarchitecture and design specs, implement and debug complex logic, and integrate IPs while supporting lint, CDC, synthesis, ECO, and front‑end integration; collaborate with SOC...

NVIDIA Corporation in Santa Clara, CA is seeking a Senior ASIC Timing Engineer specializing in DFT timing closure. You will drive timing analysis and closure for DFT logic across GPUs, CPUs, DPUs, LPUs, and SoCs at block, cluster, and full‑chip levels, collaborating with PD, DFX, clocks teams to set timing constraints and guide convergence.The ideal...

As part of our Silicon Engineering group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processors! You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. You will collaborate with a variety of fields including Architecture, RTL, Synthesis,...