Senior Design Verification

The application window is expected to close on 1/10/2025This role can sit in our Milpitas/San Jose office location, or remotely in Austin, TX. What You'll Do: It used to be that high-speed packet forwarding was performed in dedicated ASIC designs. These days we are looking to make those ASICs more general and programmable. Cisco Common...

Job SummaryWe are seeking a highly skilled Senior ASIC Verification Engineer to join our team at Apple. The successful candidate will lead the design verification front for vendor silicon, working closely with internal and external teams to review specifications, improve DV plans & methodologies, and ensure full verification coverage.About the RoleAs a...

Summary: Meta's Reality Labs (RL) focuses on delivering Meta's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Meta RL Silicon team is driving the state-of-the-art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map...

Design Verification Engineer Location: Austin,TX Duration: 6+ MonthsDescription:Rich experience in constructing highly scalability, configurability, and reusability DV/Performance verification environment.Experience in ASIC design/verification related field in IP, Subsystem or SOC levelExperience in writing System Verilog and/or System C models for...

About the RoleWe are seeking an experienced Senior Design Verification Engineer to join our dynamic team in Austin, TX. The ideal candidate will have 5-8 years of experience in semiconductor design verification and a proven track record of success in developing and executing verification plans for complex SoC designs.Key ResponsibilitiesVerify digital and...

Requirement: Verification JD:• Expert on the System Verilog and Advanced knowledge of HVL methodology (UVM)• Must setup up the verification environment, Test bench development, test plan and coding from scratch.• Experience on any of the below protocols is added advantage:o DDR/LPDDRo PCIE• Define ASIC/SoC verification strategy• Full chip TB...

Requirement: Verification JD:• Expert on the System Verilog and Advanced knowledge of HVL methodology (UVM)• Must setup up the verification environment, Test bench development, test plan and coding from scratch.• Experience on any of the below protocols is added advantage:o DDR/LPDDRo PCIE• Define ASIC/SoC verification strategy• Full chip TB...

DUTIES: Electronics engineer responsible for functional verification of audio CODECs and other mixed signal products. Detailed responsibilities include but are not limited to: verification planning, testbench development, failure analysis and resolution, coverage analysis and population, digital/mixed-signal modeling, directed/constrained random test...

The application window is expected to close on 1/10/2025This role can sit in our Milpitas/San Jose office location, or remotely in Austin, TX. What You'll Do: It used to be that high-speed packet forwarding was performed in dedicated ASIC designs. These days we are looking to make those ASICs more general and programmable. Cisco Common...

Senior Formal Verification Engineer Looking for new challenges? Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you. Correct Designs is currently seeking talented Formal Verification Engineers with experience working with a formal verification tool: Cadence Jasper, Mentor Quest...

About the Role:This Senior ASIC Verification Specialist will play a key role in developing cutting-edge silicon solutions for Blink and Ring battery-powered devices. Collaborating with a vertically integrated team, you will work on state-of-the-art SoCs that meet customer requirements.Key Responsibilities:Design and implement bit-accurate C modelsEvaluate...

THIS IS NOT AN ENTRY LEVEL ROLE - PLEASE NO RECENT GRADUATESJoin an innovative hardware startup in Silicon Valley as a Silicon Verification Engineer!Our mission is to reinvent silicon with RISC-V based computing platforms that aim to reshape the industry.You’ll collaborate with top-tier engineers to develop high-performance, energy-efficient, and scalable...

Responsibilities : Own the top-level verification for an AI/analytics accelerator. Collaborate with the design team to understand the design details and develop comprehensive verification strategies. Develop and execute test plans for complex features. Work with the software team to enable HW-SW co-simulation. Build emulation friendly test benches for...

Career Opportunities at Cirrus LogicCirrus Logic is a world leader in analog and mixed-signal solutions for the audio and automotive markets. We are committed to delivering innovative products that meet the evolving needs of our customers.Job OverviewWe are seeking an experienced Analog Mixed Signal Verification Engineer to join our team. The successful...

Job Title: Design Verification Consultant (GLS)Location: Bay Area,CA/Austin,TX(Onsite)Job Type: ContractJob Description• Minimum 6 years in DV domain• Good experience in verification life cycle/flow• Good understanding of SV/UVM methodology• Minimum 1 year experience in gate level simulations (GLS)• Good understanding of the GLS flow, debugging...

Job Title: Design Verification Consultant (GLS)Location: Bay Area,CA/Austin,TX(Onsite)Job Type: ContractJob Description• Minimum 6 years in DV domain• Good experience in verification life cycle/flow• Good understanding of SV/UVM methodology• Minimum 1 year experience in gate level simulations (GLS)• Good understanding of the GLS flow, debugging...

**Job Summary:**We are seeking a highly skilled Design Verification Engineer to join our team at Meta Reality Labs. As a member of our silicon validation team, you will play a crucial role in ensuring the quality and reliability of our custom silicon designs.**About Meta Reality Labs:**Meta's Reality Labs is driving innovation in augmented reality (AR)...

Job Description Picture yourself developing advanced electronic systems deployed to protect members of our armed services on some of the nation's most sophisticated aircraft. Pretty rewarding, right? And now imagine doing that job while working in a fast-paced environment using state-of-the-art tools and methodologies, all the while increasing your...

JOB TITLE: Sr. Engineer - Front-End Infrastructure / CAD (FE Design Verification) LOCATION: Austin, TX - HYBRID DURATION: 6 months PAY RANGE: $85-$125/hr COMPANY: Our client, a multinational electronics company is recruiting for a Senior Engineer - Front-End Infrastructure / CAD (FE Design Verification). If you meet the qualifications listed, please Apply...

Job Title: Design Verification Consultant (GLS)Location: Bay Area,CA/Austin,TX(Onsite)Job Type: ContractJob Description• Minimum 6 years in DV domain• Good experience in verification life cycle/flow• Good understanding of SV/UVM methodology• Minimum 1 year experience in gate level simulations (GLS)• Good understanding of the GLS flow, debugging...