Sr. Verification Engineers

Location: San Jose, CA or Remote Relocation okay. H1 transfer okay. Client is in the AI space. Responsibilities: Pre-silicon correctness and quality of a multi-million gate ASIC that integrates computational accelerators and 3rd-party SoC IP blocks. SoC/Subsystem verification of embedded CPUs such as ARM/RISC-V and interconnect subsystem (including C and...

Location: San Jose, CA or RemoteRelocation okay.H1 transfer okay.Client is in the AI space.Responsibilities:Pre-silicon correctness and quality of a multi-million gate ASIC that integrates computational accelerators and 3rd-party SoC IP blocks.SoC/Subsystem verification of embedded CPUs such as ARM/RISC-V and interconnect subsystem (including C and assembly...

As a GPU Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Responsibilities • Triage regression failures and make testbench updates • Debug functional errors in RTL model using simulation and debug tools. • Maintain efficient and clean regression status •...

As a GPU Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Responsibilities Triage regression failures and make testbench updates Debug functional errors in RTL model using simulation and debug tools. Maintain efficient and clean regression status Develop...

As a GPU Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Responsibilities • Triage regression failures and make testbench updates • Debug functional errors in RTL model using simulation and debug tools. • Maintain efficient and clean regression status •...

Role Description This is a full-time, on-site role as a Design Verification Engineer SOC at Mirafra Technologies. As a Design Verification Engineer SOC, you will be responsible for tasks such as formal verification, RTL design, computer architecture, functional verification, and debugging. Your work will contribute to the development and validation of...

About InnoPhase IoT If you are keen to work with a bunch of brilliant people with various backgrounds, if you share the same value of working smart and celebrating successes, if you have enthusiasm for big technology in a small company, if your goals are to learn and experience different aspects of worknot just singing the same song every day, you'll find...

Design Verification Engineer - Remote / San Jose, CADuration – 6 months + (can be extended longer)San Jose, CA / Remote Design Verification EngineerUVMSystem VerilogTest Bench DevelopmentSystemC (preferred) strong C/C++

Design Verification Engineer - Remote / San Jose, CADuration – 6 months + (can be extended longer)San Jose, CA / Remote Design Verification EngineerUVMSystem VerilogTest Bench DevelopmentSystemC (preferred) strong C/C++

Design Verification Engineer - Remote / San Jose, CADuration – 6 months + (can be extended longer)San Jose, CA / Remote Design Verification EngineerUVMSystem VerilogTest Bench DevelopmentSystemC (preferred) strong C/C++

As a GPU Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Responsibilities • Triage regression failures and make testbench updates • Debug functional errors in RTL model using simulation and debug tools. • Maintain efficient and clean regression status •...

Design Verification Engineer – San Jose, CA Acceler8 Talent is currently seeking a skilled Design Verification Engineer to join one of the world's leader in AI innovation, that specializes in the design of high-performance, low-power AI inference solutions.You'll play a key role by ensuring their perception software sees the road correctly, collaborating...

Design Verification Engineer – San Jose, CA Acceler8 Talent is currently seeking a skilled Design Verification Engineer to join one of the world's leader in AI innovation, that specializes in the design of high-performance, low-power AI inference solutions.You'll play a key role by ensuring their perception software sees the road correctly, collaborating...

Company Quest Global Job Area Hardware Engineering Job Description Summary General Summary: Senior Design Verification Engineer Join the Quest Global as a Senior Design Verification Engineer for the most cutting-edge work. Quest Global assists its customers in developing their next generation flagship product lines (mobile devices, complex routers/switches,...

CompanyQuest GlobalJob AreaHardware EngineeringJob Description SummaryGeneral Summary:Senior Design Verification EngineerJoin the Quest Global as a Senior Design Verification Engineer for the most cutting-edge work. Quest Global assists its customers in developing their next generation flagship product lines (mobile devices, complex routers/switches,...

CompanyQuest GlobalJob AreaHardware EngineeringJob Description SummaryGeneral Summary:Senior Design Verification EngineerJoin the Quest Global as a Senior Design Verification Engineer for the most cutting-edge work. Quest Global assists its customers in developing their next generation flagship product lines (mobile devices, complex routers/switches,...

Who We AreThe Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco...

Who We Are The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco...

Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA ○ Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM ○ Debug RTL and Gate simulations and work with...

Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA ○ Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM ○ Debug RTL and Gate simulations and work with...