Hardware Engineer

2 months ago


San Jose, United States Tech Providers Inc. Full time
Hardware Engineer
12+ Months Contract
San Jose, CA (Onsite role)
 
Duties:              
  • Integration for STA: including Hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction.
  • Timing closure with various timing ECO including transition, setup, hold, noise, crosstalk, and power recovery.
  • Familiarity with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates.
  • This role expects you to be responsible for closing timing at block, sub-chip, and full-chip levels, performing quality checks such as setup, hold, transition, and noise, while managing ECO tasks.
  • Your role may include extraction and STA flow development, convergence strategies.
 
Skills:  
  • Degree in Electrical Engineering or Computer Engineering.
  • 8+ years of ASIC STA (Static Timing Analysis) experience.
  • Candidate will be using following tools and must possess below experience of tools: Synopsys Design Compiler/ Synopsys Primetime/ Cadence Tempus
  • Synthesis Tools: Synopsys DC/DCG/FC.
  • Static Timing Analysis & ECO: Synopsys Primetime/PTPX/Tweaker/Prime Closure, Cadence Tempus.
  • Scripting: TCL, Perl, or Python.
 
Education:       
  • BS/MS in Engineering.


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