Sr. SOC/ASIC Physical Verification Engineer
Found in: Talent US C2 - 1 week ago
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
SR. SOC/ASIC PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING)
At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to 2M+ users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
Develop and support block and full chip automated physical verification (PV) flows and scriptsPerform block and full chip physical verification and work with physical design (PD) team to close design issuesExecute SOC GDSII integration, seal ring addition and tapeout collateral generation to send to the foundryWork closely with semiconductor foundries on installation, maintenance of process design kits (PDKs) for SOC physical design teamsBe the bridge between physical design team and the foundry, doing PV electronic design automation (EDA) tool support across all silicon projectsBASIC QUALIFICATIONS:
Bachelor’s degree in electrical engineering, computer engineering or computer science5+ years of experience working with block or full chip physical verification, voltage drop and/or power/signal electromigration analysisPREFERRED SKILLS AND EXPERIENCE:
Experience in industry standard physical verification EDA toolsExperience in developing block and full chip physical verification flows for Design Rule Check (DRC)/Layout Versus Schematic (LVS)/Antenna (ANT)/Electrical Rule Check (ERC)/Design for Manufacturing (DFM)/Electrostatic Discharge (ESD) etc.Experience in top-level integration of connectivity, system bus, peripherals and CPU IP Experience in ASIC physical design and strong experience in mixed-signal IP integrationProficiency in writing Linux shell scripts and general programming (e.g., Perl, shell, TCL and/or Python)Experience working with foundry, installing PDKs, libraries, IPs and setting up design environments for PD teamsStrong knowledge of deep sub-micron FinFET technology nodes (7nm and below)Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environmentADDITIONAL REQUIREMENTS:
Must be willing to travel when needed (typically-
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