ASIC Synthesis Engineer
Found in: Appcast Linkedin GBL C2 - 2 weeks ago
Must-haves
Following is the Job Description:
10+ years of experience
Knowledge of the ASIC design flow, synthesis, static timing analysis, scripting, and netlist generation
Expertise in STA tools(PrimeTime) and flow
Proficient in the closure of end-to-end logic equivalence (FV, LEC) with functional ECOs in the mix
UPF usage for power and voltage islands
Logic synthesis execution using physically aware techniques in single-digit process nodes using Design Compiler, Fusion Compiler &/or Genus
Knowledge of timing corners, operating modes, process variations, and signal integrity-related issues
Experience with scripting languages such as Tcl, Perl, Unix shells and Makefiles
Strong problem-solving skills and methodical work practices
Day-to-Day
Responsibilities
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This position is for an ASIC/Mixed Signal Design Engineer that will be responsible for the design, verification, documentation and support of various types of complex IP
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This ASIC/mixed signal design engineer will be responsible for the design, verification and support of complex IP used in the development of Broadcom's ASIC products
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The engineer will need to work independently as was well as part of the larger development team
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The engineer will need to be familiar with all aspects of the design flow
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This will include, but is not be limited to, design implementation (RTL/Verilog), synthesis, static timing and design audits (LINT, CDC)
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The engineer will work closely with the other design, verification, modeling and physical design engineers
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Design and implement digital/mixed-signal circuits
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Verification of digital/mixed-signal circuits
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Physical synthesis and static timing constraint development and analysis
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Documentation including but not limited to design guides, verification plans, audit reports, design reviews
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