Elect Design and Analy Engr 3
3 weeks ago
Location: El Segundo, CA
Hourly rate: $61.00 - $66.00
Contractor benefits: Medical, Vision, Dental, 401k
Candidate must have UVM experience.
Create UVM simulation plan from design specification.
Create or modify UVC, Score Board, Monitor, and test cases.
Verify until functional coverage and code coverage meet project threshold.
Document results.
Required:
Bachelor's degree in Engineering.
5+ years of experience as an ASIC/FPGA Design Verification Engineer.
1-2 years of UVM tool.
Cadence Xcelium verification tool.
Must be U.S. Person for purposes of Export Compliance.
#MWL
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