Electrical Design
2 weeks ago
**Job Title: Elect Design and Analy Engr/ASIC/FPGA Design Verification Engineer**
**Location: El Segundo, CA**
**Duration: 6 Months**
- Create UVM simulation plan from design specification. Create or modify UVC, Score Board, Monitor, and test cases. Verify until functional coverage and code coverage meet project threshold. Document results.
- ASIC/FPGA Design Verification Engineer with UVM Experience
- 5+ years of experience
- 1-2 years of UVM tool
- Cadence Xcelium verification tool
**Education / Experience**:
- Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 5 or more years' related work experience or an equivalent combination of technical education and experience (e.g. PhD, Master+3 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.
**Job Type**: Contract
Pay: $30.00 - $70.00 per hour
Expected hours: 40 per week
**Benefits**:
- 401(k)
- 401(k) matching
- Dental insurance
- Health insurance
- Life insurance
- Paid time off
- Vision insurance
Schedule:
- 8 hour shift
- Monday to Friday
**Experience**:
- Ultraviolet-C (UVC): 5 years (required)
Ability to Relocate:
- El Segundo, CA: Relocate before starting work (required)
Work Location: On the road
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