Verification Engineer

6 days ago

Austin, Texas, United States Peach HR Full time $120,000 - $180,000 per year

We are assisting one of our clients with a direct hire role.

For qualified candidates our client will consider H1-B sponsorship

Our client is a Series-D semiconductor innovator specializing in programmable coherent DSP (Digital Signal Processing) solutions for cloud and AI infrastructure—a foundational technology enabling faster, more efficient data transmission within and between AI data centers.

Recently emerging from stealth with $180M in funding, the company is backed by top-tier venture investors including Kleiner Perkins, Spark Capital, Mayfield, and Fidelity Investments.

The firm is shaping the future of AI infrastructure and cloud connectivity through cutting-edge DSP innovations

About The Position:

For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Senior Verification Engineer to be driving into the complicated RTL design verification activity on various design aspects.

You'll be part of a pioneering company at the at the forefront of next-gen optical communication systems (800G, 1.6T, and beyond), working alongside seasoned industry leaders and engineers.

This is an exceptional opportunity to influence the architecture of AI connectivity and shape the technologies driving modern data infrastructure.

Responsibilities:

Plan and perform the verification of digital design blocks according to the design specification and interacting with design engineers.

Build verification environments using SystemVerilog and UVM.

Identify and write all types of coverage measures for corner-cases.

Debug the functionality with design engineers.

Perform coverage collection and follow the metrices to close the full functionality.

Requirements
:

5+ years of experience – a must

At least 3 years of Verification experience

Performed at least 1 or more full block/system verification cycles.

In depth knowledge in VLSI verification flow, languages and concepts.

Experience in data path or data protocols, specifically Ethernet – preferred

Verification using one of the known methodologies (eRM, UVM, OVM).

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