Lead Senior Verification for DFT

1 week ago

San Jose, California, United States Tara Technical Solutions (TTS) Full time $120,000 - $180,000 per year

2 New Lead Verification for DFT Opportunities.

Full-Time- Direct Hire with our Fortune 500 Client- San Jose.

*** Sr.Staff or Principal or Lead Levels are available

Verification Lead for DFT Engineer position at our San Jose.

Assist with HBM, DDR and SerDes designs through comprehensive Design for Test (DFT) verification strategies.

Work with cross-functional teams to develop, implement, and validate DFT methodologies, guaranteeing that our products meet the highest quality standards.

Key Responsibilities:

Implement and verify DFT methodologies specifically for HBM, DDR and SerDes designs.

Collaborate with design and architecture teams to identify and define critical testability requirements.

Utilize advanced simulation tools and methodologies to thoroughly verify DFT implementations.

Analyze DFT-related data and provide insights for continuous design improvements.

Document verification processes, results, and best practices to enhance team knowledge and efficiency.

Stay updated with the latest trends and technologies in DFT, HBM, and SerDes to drive innovation within the team.

Working closely with STA and DI Engineers design closure for test

Generating, Verifying & Debugging Test vectors before tape release.

Validating & Debugging Test vectors on ATE during the silicon bring up phase

Assisting with silicon failure analysis, diagnostics & yield improvement efforts

Working closely with I/P DFT engineers & other stakeholders

Debugging customer returned parts on the ATE

Innovating newer DFT solutions to solve testability problems in 3nm IPs & beyond.

Automating DFT & Test Vector Generation flows.

Skills/Experience:

Strong DFT background (such as Analog DFT, MBIST, IEEE1687 and others)

Proven experience in DFT verification, particularly with HBM, DDR, PCIE and other SerDes IPs.

Understanding of DFT methodologies, including scan, BIST, and ATPG.

Proficiency in simulation tools and scripting languages (e.g., Perl, Python, TCL and ruby).

Excellent problem solving, debug , root cause analysis and communication skills

Experience working on ATE is a plus.

Familiarity with BIST logic for array and link testing is a plus

Knowledge of AHB/APB/AXI buses is a plus

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