Processor ASIC RTL Design Engineer

CompanyQualcomm Technologies, Inc.Job AreaEngineering Group, Engineering Group > DSP Architecture and DesignGeneral SummaryA variety of high performance, low power Hexagon/NPU cores are at the heart of Qualcomm's multi-tier mobile SOC, Server IoT, Automotive roadmap. The Hexagon architecture is designed to deliver performance with low power and area over a variety of applications like Audio, Modem, AI, IoT and Automotive.This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced technologies. The successful candidate will possess detailed understanding of RTL design, synthesis, static timing analysis, PLDRC, clock domain crossing, and low power techniques. Knowledge and experience of microprocessor design and integration is a definite advantage.The Job Responsibilities IncludeWork with system architecture team to define micro-architecture documentation for various blocks in Hexagon/NPU and sub-systemDevelop RTL for multiple logic blocks of Hexagon/NPU and sub-system for SoC integrationRun various frontend tools to check for linting, clock domain crossing, power intent etcWork with physical design team on design constraints and timing closureWork on area and power optimizationWork with verification team to collaborate on test plan, test debug, coverage plan and coverage closureSupport internal hardware integrationProvide ideas and further the innovation of ASICs, IP cores, and process flowsPreferred Qualifications2+ years of practical experience with details of RTL development including:functional and structural RTL design in system Verilog, design partitioning, simulation and regression, collaboration with design verification team. Familiar with latest design tools (such as linting, CDC, LEC, CLP etc)Experience With The Following Disciplines Is Highly DesirableProcessor integrationBus interfaceComputer architectureKeywordsRTL, processor, Verilog, System Verilog, logic design, digital design, processor integration, bus interface, cache.Minimum QualificationsBachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 2+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.ORMaster's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 1+ year of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.ORPhD in Electrical Engineering, Computer Science, Computer Engineering, or related field.2+ years of experience with high-performance microprocessor design.Qualcomm is an equal opportunity employer. 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Qualcomm is not responsible for any fees related to unsolicited resumes/applications.EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.Pay Range And Other Compensation & Benefits$127, $190,800.00The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. 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