Digital Verification Engineer
4 weeks ago
Job Summary
We are seeking a talented digital verification engineer to join our team at Northrop Grumman. As a staff digital verification engineer, you will be responsible for developing and implementing digital verification methodologies and tools to support the design and verification of complex digital systems.
Key Responsibilities
- Develop and implement digital verification methodologies and tools to support the design and verification of complex digital systems
- Collaborate with cross-functional teams to integrate verification solutions into the design flow
- Design and develop testbenches and constrained-random testbenches for digital systems
- Develop and maintain intellectual property (IP) blocks and interfaces for digital systems
- Develop and maintain verification plans and status reports
Requirements
- Bachelor's degree in a technical area (BSEE or other Engineering discipline preferred) with 12 years of relevant experience (10 years with technical MS; 7 years with PhD)
- Experience in HDL (VHDL/Verilog) and HVL (SystemVerilog)
- Experience with SystemVerilog Assertions (SVA)
- Knowledge of Universal Verification Methodology (UVM)
- Familiarity with a coverage-driven verification methodology from planning through closure
- Knowledge of industry standard interfaces
- Experience with object-oriented programming languages and concepts
Preferred Qualifications
- Advanced Degree either MS or PhD
- Experience with Mentor Graphics and/or Cadence Verification tools - FPGA/ASIC Design experience
- Experience with scripting languages (Bash, Perl, Python, Tcl)
- Current TS/SCI security clearance with Polygraph
What We Offer
- Competitive salary range: $173,200 - $259,800
- Discretionary bonus and Long Term Incentives
- Health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business
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